Sr. Staff Design Engineer

Credo•Pittsburgh, PA

1d•$144,000 - $228,000

About The Position

Team Credo is seeking a Sr. Staff Design Engineer to drive hands-on digital ASIC design and strategic architecture direction for its High-Performance Network Interface IP portfolio. The role influences interconnect infrastructure for next-generation AI and HPC systems. Depending on the candidate’s strengths, the work may range from leading RTL development and design execution to shaping product roadmaps, architecture requirements, and long-range technology investments. The position calls for deep expertise in computing and communication systems, including memory subsystems, inter- and intra-chip interconnects, Ethernet, CXL, PCIe, UCIe, and UALink, and an understanding of how these technologies support scalable AI infrastructure across accelerator, chiplet, and data center environments. The role combines product and technology strategy with design execution. It includes evaluating RFQs and technical tradeoffs, defining roadmaps and requirements, planning and tracking design activities and releases, developing and debugging RTL, supporting synthesis and timing closure, and partnering with verification and cross-functional teams. The position is eligible for a discretionary bonus, equity, and medical and other benefits. Base salary range is $144,000–$228,000 per year; the offer depends on factors including education, experience, training, skills, qualifications, and location.

Requirements

Eight or more years of experience.
Bachelor’s or master’s degree in electrical engineering, computer engineering, or a related field.
Strong track record of technical leadership, including the ability to plan, manage, and influence engineering, product, and business stakeholders.
Digital design expertise in state machines, data paths, FIFOs, asynchronous crossings, clock and reset concepts, and high-speed and low-power design.
Experience using Verilog/SystemVerilog and synthesizable design concepts targeting deep sub-micron nodes.
Comprehensive understanding of how architecture affects logic synthesis, timing closure, and physical implementation.
Deep knowledge of networking protocols, including 802.3 Ethernet, PCIe, CXL, UCIe, UALink, and related standards.
Knowledge of inter- and intra-chip buses and fabrics, including NoC, coherent and non-coherent fabrics, arbitration, flow control, and latency/bandwidth optimization.
Knowledge of FEC algorithm theory and basic data communication theory.
Systems thinking to evaluate technical tradeoffs and translate them into product direction and prioritized requirements.
Excellent communication skills for presenting complex concepts, driving alignment, and producing clear requirements and strategy documents.
Advanced debugging skills.
Unix/Linux scripting experience with Perl, Tcl, Python, and shell.
Experience using Cadence, Mentor, and Synopsys tools for simulation, lint, and synthesis.

Nice To Haves

Knowledge of AI infrastructure or AI workloads.
UVM and constrained-random testing experience.

Responsibilities

Lead technical evaluations of RFQs and guide functionality, power, performance, and area tradeoffs.
Partner with product marketing and key customers to define technical solutions across product generations.
Help define product and technology roadmaps based on customer needs, market direction, and technical trends.
Translate standards, constraints, and ecosystem trends into architecture goals, requirements, and engineering priorities.
Own scoping, planning, and execution tracking for design activities and product releases.
Guide architectural decisions with attention to outcomes, scalability, product impact, and implementation efficiency.
Create functional specifications, architecture and microarchitecture documents, and product requirements.
Develop, debug, and enhance RTL; run lint checks and simulations.
Perform synthesis tasks, including timing constraints, logic synthesis, report analysis, timing closure, and ECOs.
Partner with verification teams to shape test plans, review results, and lead root-cause analysis and failure resolution.
Lead and contribute to design reviews to ensure technical rigor and design quality.
Identify risks, dependencies, and roadmap gaps early and drive cross-team mitigation.
Align engineering, product, and business teams on customer needs, differentiation, and execution.
Communicate technical strategy, priorities, and rationale to internal and external stakeholders.