PLL Design Engineer

Apple • Cupertino, CA

1d

About The Position

Apple is hiring a PLL Design Engineer for its Analog-Mixed/Signal group. The role focuses on developing high-quality hard IPs and cutting-edge frequency synthesizers for Compute, SoC, SerDes, and Cellular applications. The engineer will work on complex SOC/PHY designs and projects with tight production schedules, collaborating with colleagues to solve problems and contribute to Apple’s technology and product innovation.

Requirements

• BSEE with at least 10 years of relevant experience.
• Demonstrated proficiency in PLL/FLL and frequency-synthesis architecture and circuit design, including digital and analog approaches.
• Experience with DCO/VCO design, including ring-oscillator and LC designs, Fractional-N, SSC, and spur and jitter cancellation techniques.
• Good understanding of band gaps, bias circuits, op-amps, LDOs, feedback, and compensation techniques.
• Deep understanding of clocking fundamentals, phase noise, jitter analysis and budgeting, and feedback-loop dynamics.
• Skill in developing SystemVerilog models and performing behavioral simulations to explore architectural performance and impact on loop dynamics.
• Exceptional attention to detail and ability to understand problems and their systemic impacts.
• History of innovation and self-directed learning, demonstrated leadership skills, and a growth mindset.
• Strong teamwork capabilities, productivity, and scripting skills.

Nice To Haves

• Ability to design and debug RTL.
• Experience using industry-standard design tools.

Responsibilities

• Develop frequency synthesizers for Compute, SoC, SerDes, and Cellular applications.
• Design PLL/FLL and frequency-synthesis architectures and circuits.
• Develop SystemVerilog models and perform behavioral simulations to evaluate architectures and their effects on loop dynamics.
• Understand problem details and systemic impacts to support thorough problem-solving.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior