Principal PLL Design Engineer

Celero Communications • San Jose, CA

20h

About The Position

The Principal PLL Design Engineer will architect and design phase-locked loops for next-generation optical transceivers, high-speed SerDes, and ADC/DAC systems. The role focuses on high-speed CMOS analog PLL design for next-generation interconnect technology supporting AI applications, with responsibility for transistor-level analog and mixed-signal design, simulation, layout oversight, lab bring-up, performance characterization, and system-level validation.

Requirements

• Master’s degree and/or PhD in Electrical Engineering or a related field.
• At least 5 years of relevant PLL design experience.
• Production-level tape-out experience.
• Extensive experience with advanced-node technologies, including 16nm/12nm, 7nm, 5nm, 3nm, or 2nm processes.
• Deep understanding of phase-noise analysis, VCO design, LDOs, and supporting PLL circuitry.
• Proficiency with Cadence Virtuoso, an electromagnetic simulator such as EMX or HFSS, and MATLAB for system-level modeling.
• Strong communication and documentation skills.

Responsibilities

• Evaluate trade-offs among PLL topologies, including integer-N, fractional-N, and all-digital PLLs, to meet power, area, jitter, and frequency-range specifications.
• Architect, design, and simulate analog/mixed-signal PLL building blocks at transistor level, including VCOs, charge pumps, dividers, PFDs, and loop filters.
• Address advanced-node challenges such as self-heating, electromigration, VCO linearization, and device-level noise optimization.
• Supervise and verify layouts produced by layout engineers, focusing on floorplanning, matching, and parasitic minimization.
• Lead PLL bring-up in the lab and conduct performance characterization using state-of-the-art lab equipment.
• Conduct system-level simulations and validation for PLL integration into advanced transceiver technologies.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal