Principal Place and Route (PnR) Engineer

SambaNova Systems • San Jose, TX

10d

About The Position

SambaNova’s Place and Route team develops software that maps dataflow graphs onto its Reconfigurable Dataflow Unit (RDU). The tools partition graphs, place them on the chip’s compute and memory units, and route communication between them. The quality of this mapping affects compiled-program throughput, including for large language model inference and training.

In this role, you will develop and tune the partitioning, placement, and routing algorithms used to map customer workloads onto the RDU. You will collaborate with compiler, hardware architecture, and performance engineering teams to model hardware constraints and investigate throughput gaps. Your work will ship in production releases and affect measured performance.

Requirements

• M.S. or Ph.D. in Computer Science, Computer Engineering, or a related field.
• At least 3 years of experience developing optimization or graph algorithms in industry or research.
• Expert knowledge of graph algorithms, partitioning algorithms, combinatorial optimization, or MILP solvers.
• Strong proficiency in C/C++.
• Familiarity with Python.
• Experience designing large, highly parallel, performance-sensitive systems.
• Ability to learn hardware architecture and apply it to improve performance.
• Experience solving NP-hard problems in practice using heuristics, approximation, or pruned exact methods.

Nice To Haves

• Experience with place and route for FPGAs, CGRAs, or other spatial architectures.
• Experience with ML compilers such as MLIR, LLVM, TVM, or XLA.
• Experience with simulated annealing, constraint programming, or SAT/SMT solvers.
• Familiarity with LLM inference stacks such as vLLM and PyTorch.
• Publications at venues such as FPGA, DAC, ICCAD, or MLSys.

Responsibilities

• Develop partitioning, placement, and routing algorithms that meet hardware resource constraints while keeping compile times practical.
• Tune PnR results for target workloads, including LLM inference at different batch sizes and concurrency levels.
• Model new hardware constraints and architecture features in solvers and heuristics as the chip evolves.
• Analyze compiled output with performance engineers and trace throughput gaps to mapping decisions.
• Build infrastructure for prototyping, regression testing, and deploying PnR changes.
• Work with compiler and hardware teams to define interfaces and resource models.

Benefits

• Equity and benefits as part of a competitive total rewards package.
• Employer covers 95% of employee medical insurance premiums and 77% of dependent premiums.
• Health Savings Account (HSA) with employer contribution.
• Dental, vision, short- and long-term disability, basic life, voluntary life, and AD&D insurance plans.
• Flexible Spending Account (FSA) options for health care, limited purpose, and dependent care.
• Headspace subscription.
• Gympass+ membership with access to physical gyms.
• One Medical membership.
• Counseling services through an Employee Assistance Program.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior