Physical Designer Engineer, Synthesis/PnR

Rivian•Palo Alto, CA

10d

About The Position

As a Physical Design Engineer, you will contribute to all phases of physical design for high-performance SoCs at the block, subchip, and full-chip levels, from RTL to GDSII. You will collaborate with Foundry Process Engineering, SoC Architecture, Microarchitecture, Packaging, Signal Integrity, and Power Integrity teams to drive physical design through successful tapeout and production silicon. The role includes subchip and block-level place and route, full-chip integration, timing and power closure, EM-IR signoff, power-integrity analysis, and development of automated design flows. You will help establish process and library choices, create chip and package co-analysis models, and ensure floorplanning, clocking, power delivery, and verification meet the design requirements.

Requirements

At least 12 years of experience in the chip industry, with a track record of delivering silicon into volume production across multiple technology generations.
Proven track record defining complex SoCs across multiple technology generations.
BS, MS, or PhD in Electrical and Computer Engineering, with emphasis on Computer Architecture.
Experience in CPU architecture, preferably instruction decode or execution units.
Deep physical-design knowledge, including physical-aware synthesis, floorplanning, clock-tree implementation, routing, STA timing signoff, and chip finishing.
Experience with advanced process nodes such as 5 nm and below, including associated DRC/DFM challenges.
Knowledge of design flows from RTL to GDSII.
Solid understanding of STA, SDC, MCMM, and on-chip variation.
Good knowledge of EM-IR signoff requirements.
Experience with EDA tools such as Synopsys and/or Cadence for PPA optimization.
Scripting skills such as Python or Tcl.
Good communication, documentation, and cross-functional collaboration skills.
Teamwork and leadership qualities supported by references.

Nice To Haves

Experience with multi-SoC systems.
Knowledge of machine-learning algorithms, such as convolutional neural networks.
Extensive physical-design experience at block, subchip, and full-chip levels.
Experience with MSCTS or custom H-tree clock implementation.
Knowledge of basic SoC architecture and ability to work with front-end design teams to address timing, congestion, and power issues.

Responsibilities

Perform subchip- and block-level place and route, and close designs to meet performance, power, and area targets.
Lead and perform full-chip SoC integration, including die-size optimization, floorplanning, hard-IP integration, partitioning, clock planning, bump placement and RDL routing, power-grid generation, full-chip STA timing, DFT strategy planning, and final physical verification.
Define EM-IR signoff requirements and signoff methodology.
Define and support static and dynamic thermal, electromigration, peak-current, di/dt, and effective-resistance analyses.
Develop and support Chip-Package Co-Analysis (CPA) and on-die Chip-Power-Model (CPM) for package and die co-design analysis.
Lead EM-IR signoff and contribute successful tapeout experience.
Perform voltage-drop analysis using RedHawk or RedHawk-SC and debug voltage-drop and EM issues to identify root causes.
Work with Foundry Engineering and Microarchitecture to establish logic levels, Multi-Vt library mixes, track choices, and metal stackups.
Define EDA flows and write automation scripts for floorplanning, placement, routing, crosstalk avoidance, cell-library usage, and physical verification.
Collaborate with Microarchitecture, Signal Integrity, Power Integrity, and Thermal teams to align floorplanning and logic design with package, board-layout, and power-delivery requirements, including power domains, voltage levels, power gating, sequencing, always-on power, and hotspot mitigation.
Design floorplans that align power distribution across voltage domains with bump and bump-ball maps to support power and signal integrity.
Ensure robust clocking architecture and timing, including clock-tree synthesis, static timing analysis, timing closure, clock gating, reference clocks, PLL placement, and clock muxing.
Support parasitic extraction, LVS/DRC, and other physical, power, and post-layout timing verification checks.