Principal Place and Route (PnR) Engineer

SambaNova • San Jose, CA

11d

About The Position

SambaNova’s Place and Route team develops software that maps dataflow graphs onto its Reconfigurable Dataflow Unit (RDU). The tools partition graphs, place graph components on chip compute and memory units, and route communication between them. Mapping quality affects compiled-program throughput, including large language model inference and training.

In this role, you will develop and tune partitioning, placement, and routing algorithms for customer workloads on the RDU. You will collaborate with the compiler team, hardware architects, and performance engineers to model hardware constraints, identify throughput gaps, and improve measured performance. Your changes will ship in production releases.

Requirements

• M.S. or Ph.D. in Computer Science, Computer Engineering, or a related field.
• At least 3 years of experience developing optimization or graph algorithms in industry or research.
• Expert knowledge of graph algorithms, partitioning algorithms, combinatorial optimization, or MILP solvers.
• Strong proficiency in C/C++.
• Familiarity with Python.
• Experience designing large, highly parallel, performance-sensitive systems.
• Ability to learn hardware architecture and apply it to improve performance.
• Experience solving NP-hard problems in practice using heuristics, approximation, or pruned exact methods.

Nice To Haves

• Experience with place and route for FPGAs, CGRAs, or other spatial architectures.
• Experience with ML compilers such as MLIR, LLVM, TVM, or XLA.
• Experience with simulated annealing, constraint programming, or SAT/SMT solvers.
• Familiarity with LLM inference stacks such as vLLM and PyTorch.
• Publications at venues such as FPGA, DAC, ICCAD, or MLSys.

Responsibilities

• Develop partitioning, placement, and routing algorithms that meet hardware resource constraints while keeping compile times practical.
• Tune place-and-route results for target workloads, including LLM inference at different batch sizes and concurrency levels.
• Model new hardware constraints and architecture features in solvers and heuristics as the chip evolves.
• Analyze compiled output with performance engineers and trace throughput gaps to mapping decisions.
• Build infrastructure for prototyping, regression testing, and deploying place-and-route changes.
• Work with compiler and hardware teams to define interfaces and resource models.

Benefits

• Competitive total rewards package including base salary and equity.
• 95% premium coverage for employee medical insurance and 77% premium coverage for dependent medical insurance.
• Health Savings Account (HSA) with employer contribution.
• Dental, vision, short- and long-term disability, basic life, voluntary life, and AD&D insurance plans.
• Flexible Spending Account (FSA) options for health care, limited purpose, and dependent care.
• Headspace subscription for employees and dependents.
• Gympass+ membership with access to physical gyms.
• One Medical membership.
• Counseling services through an Employee Assistance Program.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal