Principal HBM Architecture & Circuit Design Engineer

Micron•Richardson, TX

3d•$139,000 - $308,000

About The Position

Micron Technology is seeking a Principal HBM Architecture & Circuit Design Engineer to own next-generation HBM core-die architecture and critical DRAM circuit design. The work directly affects bandwidth, power, area, thermal efficiency, and long-term reliability across advanced 3D-stacked HBM products. The engineer will drive architecture definition, circuit feasibility, and Architecture Reference Design (ARD) development, and support the design and deployment of AI-enabled solutions that improve efficiency and decision-making. The role includes defining HBM core-die architecture and DRAM circuit approaches, evaluating design trade-offs, developing and validating reliability and power-efficiency schemes, and collaborating across engineering teams to deliver designs. It also supports silicon bring-up, characterization, failure analysis, and the handoff from architecture to design. Micron lists a US base salary range of $139,000 to $308,000 per year for this full-time position. Additional compensation may include benefits, bonuses, and equity. Benefits include medical, dental, and vision plans, income-protection programs, paid family leave, paid time off, and paid holidays. The role is subject to Micron’s equal opportunity and affirmative action policies.

Requirements

Proven experience in DRAM architecture and circuit design, such as HBM, DDR, LPDDR, GDDR, or equivalent.
Strong understanding of DRAM array architecture, row and column paths, sensing, datapath, refresh, and reliability mechanisms.
Hands-on experience with SPICE-based circuit simulation tools such as HSPICE, Spectre, FineSim, PrimeSim, or equivalent.
Ability to evaluate performance, power, area, thermal, and reliability trade-offs.
Experience driving architecture decisions and cross-functional technical execution.
Strong problem-solving and communication skills.

Responsibilities

Own HBM core-die architecture, including bank and bank-group organization, array partitioning, datapath, refresh, and reliability features.
Drive critical DRAM circuit design and timing closure for row, column, sensing, and datapath paths.
Develop and optimize architecture solutions across bandwidth, power, area, thermal, and reliability trade-offs.
Define and validate refresh, row-hammer mitigation, data-retention, and power-efficient operation schemes.
Lead architecture feasibility studies using transistor-level simulation and physical implementation analysis.
Develop HBM Architecture Reference Designs (ARD), including golden schematics, timing budgets, and verification methodology.
Collaborate with Array, Datapath, ECC, TSV, PDN, Layout, Verification, and DFT teams to drive end-to-end design execution.
Support silicon bring-up, characterization, failure analysis, and architecture-to-design handoff.