Principal Design Engineer, HBM Architecture

Micron Technology • Richardson, TX

3d

About The Position

Micron Technology is seeking a highly motivated HBM Datapath Engineer for its HBM Architecture team. The team develops advanced datapath solutions for next-generation High Bandwidth Memory (HBM) products, supporting high bandwidth, power efficiency, reliability, and scalability across JEDEC and custom HBM solutions. This role architects, designs, and optimizes datapath circuitry across logic and core dies, and works with design, PHY, ECC, verification, layout, and system teams to deliver designs from concept through silicon bring-up and production.

The position includes translating specifications into robust micro-architectures; developing high-speed, low-latency datapaths; optimizing bandwidth, power, area, and timing; integrating reliability features; and driving schematic- and RTL-level implementations. The role also contributes to design reviews, documentation, and technical mentoring, and uses AI tools to carry out regular work efficiently.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field with 7+ years of relevant industry experience, or a Master’s degree with 5+ years of relevant industry experience.
• 3+ years of experience in high-speed digital datapath design in memory, SerDes, or SoC datapath.
• 2+ years of hands-on experience with digital schematic build, RTL, or mixed-signal datapath implementations.

Nice To Haves

• Strong understanding of HBM/DRAM architectures, including read/write data flow, timing, and multi-channel operation.
• Working knowledge of layout and floorplanning considerations for high-speed datapath.
• Experience with static timing analysis (STA) and timing-closure methodologies.
• Familiarity with advanced process-node challenges related to signal integrity, skew control, and power optimization.

Responsibilities

• Architect and design HBM read and write datapaths across core and logic dies, including alignment, buffering, timing, and control logic.
• Develop high-speed, low-latency datapath circuits supporting multi-channel HBM architectures and wide internal buses.
• Optimize datapath designs for bandwidth, power, area, and timing closure at advanced technology nodes.
• Design and integrate data reliability features, including parity, ECC hooks, lane redundancy, and remapping mechanisms.
• Collaborate with multifunctional teams to translate specifications into robust micro-architectures.
• Collaborate with PHY, DFT, verification, and layout teams to ensure functionality, testability, and manufacturability.
• Drive schematic-level and RTL-level datapath implementations, including clocking, gating, and reset strategies.
• Contribute to design reviews, documentation, and technical mentoring across HBM programs.
• Leverage AI tools to efficiently carry out regular work.

Benefits

• Choice of medical, dental, and vision plans.
• Programs that help protect income in the event of illness or injury.
• Paid family leave.
• Paid time off program.
• Paid holidays.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior