Principal FPGA Micro-Architect

Lattice Semiconductor•San Jose, CA

1d•$250,000

About The Position

Lattice is seeking a Principal FPGA Micro-Architect with deep expertise in programmable logic fabric design and experience delivering next-generation FPGA devices from concept through silicon. The role defines and drives the micro-architecture of FPGA fabric primitives, optimizing power, performance, area, and utilization across device families. The architect will shape next-generation FPGA designs for Physical AI, robotics, space, data centers, and edge applications. The position works across architecture, design verification, firmware, and CAD teams throughout the product lifecycle, from concept through silicon validation and post-silicon debug. It also includes developing architectural models, advancing low-power fabric design, defining software primitives and implementation strategies, and applying agentic AI methods to accelerate architectural exploration and design execution.

Requirements

MS or PhD in Electrical or Computer Engineering and 15+ years of FPGA fabric micro-architecture experience.
Track record delivering FPGA fabric primitives from architecture definition through tape-out and silicon validation.
Demonstrated ability to define software primitives and drive implementation strategy for fabric usability in customer design flows.
Deep expertise in FPGA fabric elements, including logic elements, DSP blocks, embedded memory blocks, interconnect routing muxes, carry chains, and clocking structures.
Proficiency in SystemVerilog/Verilog and SystemC/C++ architectural modeling for performance analysis and design trade-off evaluation.
Deep experience in advanced low-power design, including clock and power islands, power gating, multi-rail design, and dynamic power mode switching.
Extensive hands-on experience with silicon validation and post-silicon debug of FPGA fabric blocks, including bring-up, characterization, and root-cause analysis of fabric-level sightings.
Strong written and oral communication skills, with a history of executive-level presentations.
Successful background and reference checks and satisfactory proof of the right to work in the United States.

Responsibilities

Define micro-architecture for core fabric primitives, including programmable logic elements, DSP blocks, embedded memory blocks, interconnect routing, configuration memory, carry chains, and clocking structures.
Drive power, performance, area, and utilization optimization; assess implementation and routing feasibility; and make design trade-offs for modularity and scalability across device generations.
Develop SystemC/C++ architectural models for performance analysis and evaluation of fabric design trade-offs before RTL or schematic availability.
Lead advanced low-power fabric design, including clock and power islands, power gating, dual-rail architectures, and dynamic power mode switching.
Drive software primitive definition and implementation strategy so fabric elements map effectively to CAD tools and customer design flows.
Partner with architecture, design verification, firmware, and CAD teams through the product lifecycle, from concept to silicon validation and post-silicon debug.
Apply agentic AI methodologies to scale and accelerate micro-architecture exploration and design execution.