Principal FPGA Designer – TeraWave

BLUE ORIGIN•Seattle, WA

1d•$269,175 - $376,844

About The Position

Blue Origin is seeking a Principal FPGA Designer for its TeraWave program, a satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps for enterprise, data center, and government users. The role provides technical leadership in the design, development, and verification of complex FPGA-based systems supporting high-speed data processing, communications, and signal processing. As part of a small, nimble team, the designer will work across disciplines and own deliverables from concept through flight. The role spans the FPGA development lifecycle, including requirements, architecture, RTL design, verification, implementation, hardware integration, qualification, production, and on-orbit operations. It also includes technical leadership, mentoring, design-methodology development, and contributions to planning and risk management.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
12 or more years of hands-on FPGA design and verification experience, with demonstrated leadership at a principal or senior level.
Proficiency in VHDL, Verilog, and SystemVerilog for RTL design and simulation.
Experience with industry-standard FPGA families, including AMD Versal, IGLOO, or equivalent devices.
Demonstrated experience with synthesis, place-and-route, and timing-analysis toolchains.
Strong understanding of high-speed digital design, including signal integrity, clock-domain crossings, and SERDES-based interfaces such as PCIe and GTH/GTY transceivers.
Experience with FPGA-based digital signal processing architectures.
Familiarity with hardware/software co-design and embedded processor integration, such as with AMD Versal devices.
Demonstrated ability to close complex timing constraints and optimize resource utilization.
Experience with simulation and verification methodologies and tools.
Experience in a structured engineering environment involving configuration management, formal design reviews, and requirements traceability.
Strong written and verbal communication skills, including the ability to communicate complex technical concepts to diverse audiences.

Nice To Haves

Master's degree or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
Familiarity with space-grade design practices, including single-event effect mitigation strategies such as TMR, scrubbing, and fault detection.
Experience with high-speed communications systems or modem development in FPGAs.
Hands-on experience with formal verification tools or UVM-based constrained-random verification environments.
Demonstrated experience mentoring and technically developing FPGA engineers.
Previous experience in a space, defense, or satellite communications program environment.

Responsibilities

Lead FPGA designs through requirements capture, architecture definition, RTL design, functional simulation, synthesis, place-and-route, timing closure, and hardware bring-up.
Comply with and refine FPGA design methodologies, coding standards, and best practices.
Develop and maintain verification environments, including testbenches, constrained-random stimulus, and functional coverage models.
Partner with program stakeholders to define interfaces and ensure end-to-end system performance.
Support hardware integration and troubleshooting, including lab board bring-up and debug.
Conduct and participate in preliminary, critical, and peer-level design reviews, providing constructive technical feedback.
Mentor junior and mid-level FPGA engineers, provide technical direction, and foster engineering excellence.
Evaluate and select FPGA devices, IP cores, EDA tools, and vendor solutions to meet program requirements.
Contribute to program planning by estimating development work, identifying technical risks, and proposing opportunities and mitigation strategies.
Develop and maintain design documentation, interface control documents, and test plans in accordance with configuration management standards.
Support qualification, acceptance testing, production, and on-orbit operations as needed.
Include features supporting design for test (DFT) and design for manufacturing (DFM) in a high-volume production environment.

Benefits

Medical, dental, and vision insurance.
Basic and supplemental life insurance.
Paid parental leave.
Short- and long-term disability.
401(k) with a company match of up to 5%.
Education Support Program.
Stock options for regular employees working at least 20 hours per week.
Paid time off of up to four weeks per year based on weekly scheduled hours.
Up to 14 company-paid holidays.
Depending on role type and job level, employees may be eligible for benefits and bonuses tied to individual contributions or company results; amounts and eligibility are not guaranteed.