Principal FPGA Digital Engineer - 3

Northrop Grumman • Chandler, AZ

22d • $108,200 - $162,400 • Onsite

About The Position

Northrop Grumman Space Systems is seeking a Principal FPGA Digital Engineer to support the Electro-Optics (EO) Group within the Launch Vehicles business unit in Chandler, Arizona. The engineer will work with senior FPGA engineers and cross-disciplinary hardware, algorithms, and software teams to address design challenges and ensure effective hardware integration. The role focuses on developing and executing test benches that independently validate FPGA designs for functional correctness and timing requirements while following internal design standards. It involves generating, verifying, and integrating I/O and image-processing HDL modules, including function definitions, HDL coding, module-level simulation, and integration with the overall device architecture. The engineer will also manage multiple FPGA bitstream build configurations, maintain design documentation, and keep current with evolving FPGA technologies, tools, and industry methodologies. The role requires the ability to obtain a U.S. Government DoD Secret security clearance.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related discipline and 5 years of relevant experience; alternatively, a master’s degree and 3 years of experience, or a PhD and 1 year of experience.
• Ability to obtain a U.S. Government Department of Defense Secret security clearance at the time of application.
• Solid background in FPGA/SoC design, including complex firmware development using VHDL (preferred) or Verilog.
• Significant experience with AMD Xilinx FPGAs and SoCs.
• Knowledge of design constraints for timing, power, and I/O, and static timing analysis using Vivado IDE.
• Proficiency in developing, verifying, and debugging MOSA interfaces and buses, including Ethernet, PCIe, AXI4, UART, and SDLC.
• Competency with simulation tools such as Questa/ModelSim and hardware debugging tools such as logic analyzers and oscilloscopes.
• Experience creating and executing verification plans using simulation, analysis, and hardware bench testing.
• Understanding of OSVVM or UVM.

Nice To Haves

• MS or PhD in Electrical Engineering, Computer Engineering, or a related discipline.
• Active U.S. Government DoD Secret security clearance at the time of application.
• Experience with missile systems, seeker systems, or other high-reliability, environmentally challenging electro-optical applications.
• Previous experience or knowledge of DoD missile defense programs and associated standards.
• Direct experience with AMD Xilinx Versal Gen 2 or Gen 1.
• Advanced experience with Vivado IDE and Vitis Unified IDE.
• Experience designing, integrating, and verifying DDR memory interfaces (such as DDR3, DDR4, or DDR5) and fabric-based controllers (such as AXI or custom interconnects), including IP configuration, timing closure, signal integrity, and high-throughput data movement.
• Understanding of embedded C/C++ programming for processor/SoC integration.
• Knowledge of high-speed PCB design and signal integrity.
• Strong experience with OSVVM or UVM.
• OSVVM is preferred.

Responsibilities

• Collaborate with senior FPGA engineers and multidisciplinary hardware, algorithms, and software teams to resolve design and integration challenges.
• Develop and execute advanced test benches to verify FPGA designs against functional and timing requirements.
• Generate, verify, and integrate I/O and image-processing HDL modules, including function definitions, HDL coding, module-level simulation, and integration with the overall device architecture.
• Ensure compliance with internal design standards throughout the development lifecycle.
• Oversee configuration management of multiple FPGA bitstream build configurations for different use cases or platform requirements.
• Prepare, present, and maintain design documentation, including schematics, simulation results, and verification reports.
• Stay current with evolving FPGA technologies, tools, and industry methodologies.

Benefits

• Health insurance coverage.
• Life and disability insurance.
• Savings plan.
• Company-paid holidays.
• Paid time off (PTO) for vacation and/or personal business.
• Depending on the position, employees may be eligible for overtime, shift differential, and a discretionary bonus.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal