Principal Engineer, FPGA Architecture
About The Position
The research team identifies data movement bottlenecks in AI systems and addresses them through new memory and storage SoC architectures, proving concepts on FPGA with real AI workloads. The Principal Engineer defines SoC block architecture and microarchitecture, analyzes AI workloads such as LLM inference, and develops and evaluates hardware architectures to improve memory, storage, and network data movement. The role involves designing and debugging high-speed interfaces and data paths, validating prototypes through simulation and lab testing, integrating prototypes with host software and infrastructure, and assessing performance, power, and cost trade-offs. The engineer leads research from problem definition through publications, patents, and conference presentations. This position requires daily onsite presence at the Folsom office/headquarters.
Requirements
- Bachelor of Engineering, BS, MS, or Ph.D. in Computer Engineering, Electrical Engineering, or Computer Science; BS/MS/Ph.D. preferred.
- 10+ years of work experience in architecture development.
- Strong SystemVerilog RTL design and debug skills.
- Proven FPGA timing-closure experience on large, high-speed designs.
- Hands-on experience with at least one high-speed interface: Ethernet, PCIe, or DDR/LPDDR.
- Self-motivated problem solver able to work well in a team.
- Comfort defining problems, forming hypotheses, and validating them with experiments.
- Inclusive and adaptable approach when working with diverse people and global norms.
- Curiosity, resilience, and willingness to use data to build understanding.
- Collaborative approach to building relationships, offering support, and welcoming others' approaches.
- Proactive, creative approach to exploring ideas and adapting to change.
Nice To Haves
- Interest in AI infrastructure and data systems.
- Research publications.
- Experience in storage systems such as NVMe/SSD, networking systems such as RDMA/RoCE, or memory systems such as CXL.
Responsibilities
- Define architecture and microarchitecture for SoC blocks and prototype them on FPGA.
- Analyze AI system workloads, such as LLM inference, to identify memory, storage, and network bottlenecks.
- Propose and evaluate novel hardware architectures that address bottlenecks more efficiently than existing solutions.
- Design, implement, and debug high-speed interfaces such as Ethernet, PCIe, and memory interfaces.
- Build high-throughput data paths with efficient buffering and flow control.
- Develop simulation- and lab-based validation, including stress and error-injection testing.
- Integrate prototypes with host software, servers, and network equipment.
- Analyze performance, power, and cost trade-offs and translate results into SoC requirements.
- Lead research from problem definition through publication, patents, and presentations at top-tier conferences.
Benefits
- Medical, dental, and vision benefits.
- 401(k).
- Incentive opportunities based on individual and company performance.
- Charitable giving match and opportunities to participate in community activities.
- 4+ weeks of paid time off annually, plus holidays and sick leave.
- Fertility care or adoption stipend, caregiver support, and medical travel support.
- On-demand wellness apps and free confidential therapy sessions.
- Onsite café and gym, plus virtual fitness classes.
- Flexible work environment.
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What This Job Offers
Job Type
Full-time
Career Level
Principal
