Principal Engineer, Design Verification
About The Position
As part of Marvell’s Design Verification Team, the Principal Engineer will verify circuitry in chips for general-market and customer-specific applications. These chips support high-speed data transfers and must meet customer specifications. The role works on verification of AI/ML, network processing, compute, memory expander, and accelerated compute SoCs and IPs. It includes developing verification plans and functional verification environments, creating reference models and bus-functional monitors and drivers using SystemVerilog and UVM, writing tests using random techniques and coverage analysis, debugging failures with designers, and maintaining tools for state-of-the-art multicore SoCs. The role also provides technical mentorship to a verification team across multiple geographies.
Requirements
- Master’s degree, or foreign equivalent, in Computer Science, Electrical Engineering, or a related field.
- Five years of experience in the job offered or a related occupation.
- Five years of experience developing complex/random verification environments using SystemVerilog/UVM.
- Five years of experience writing and executing detailed verification test plans.
- Five years of experience with scripting languages such as Python or Perl, EDA verification tools, bug tracking, and regression mechanisms.
- Five years of experience with object-oriented design and implementation.
- Five years of experience with verification of subsystems such as ARM/processor, memory, networking, NoC, and cache designs.
- Five years of experience with protocols such as PCIe, Ethernet, DDR, and HBM.
- Five years of experience with C/C++ for modeling and code development to run on ARM/processors.
- Five years of experience with version control systems including CVS, Perforce, and Git.
- Five years of experience with low-speed I/O interfaces including SPI, UART, I2C, I3C, and JTAG.
- Five years of experience with bus/interconnect protocols including AXI, ACE, AHB, APB, and NIC-400.
- Five years of experience with ASIC development processes, tools, and methodologies.
- Five years of experience analyzing complex systems, SoC architecture, memory, and peripheral interfaces.
- Applicants must be eligible to access export-controlled information under applicable law; applicants may be subject to an export license review process.
Responsibilities
- Develop verification plans for complex designs.
- Verify AI/ML, network processing, compute, memory expander, and accelerated compute SoCs and IPs.
- Develop functional verification environment architecture, including reference models and bus-functional monitors and drivers using SystemVerilog and UVM.
- Develop verification test plans and write tests using random techniques and coverage analysis, collaborating with designers to ensure completeness.
- Develop tests and tune the verification environment to achieve coverage goals.
- Debug failures and work with designers to resolve issues.
- Architect, develop, and maintain tools to streamline the design of state-of-the-art multicore SoCs.
- Technically mentor a verification team across multiple geographies.
Benefits
- Eligible to participate in Marvell’s bonus and equity plans, including a new-hire equity grant and annual equity refreshers.
- Competitive compensation and great benefits.
- Resources and opportunities to grow and develop.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
