Principal Design Engineer

Microsoft•Raleigh, NC

13h

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) supports Microsoft’s cloud infrastructure and Intelligent Cloud mission. The Artificial Intelligence System on Chip (AISoC) team helps define and deliver operational measures of success for hardware manufacturing, with a focus on planning, quality, delivery, scale, and sustainability for Microsoft cloud hardware. The team is seeking a Principal Design Engineer to develop high-performance silicon designs, custom intellectual property, and System-on-Chip designs for AI components. The role is part of the digital logic design team and focuses on microarchitecture-based functions and features. The engineer owns logic design and RTL implementation for high-performance digital IP, drives design quality, supports timing closure, and collaborates with verification, physical design, design-for-test, and other engineering teams. The position also provides technical leadership through mentorship and collaboration.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 3+ years of technical engineering experience; or a master's degree in one of these fields and 6+ years of technical engineering experience; or a bachelor's degree in one of these fields and 8+ years of technical engineering experience; or equivalent experience.
Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
Must satisfy export-control eligibility requirements and provide citizenship or qualifying residency/protected-status documentation; citizenship will be verified with a valid passport, with other applicable documents permitted for lawful permanent residents, refugees, and asylees.

Nice To Haves

15+ years of experience in logic design delivering complex solutions.
10+ years of experience in floating point arithmetic and datapath design, DMA design, subsystem designs/integration, or custom logic design.
5+ years of experience leading logic design teams.
Multiple successful ASIC tape-outs in deep sub-micron technologies.
Experience with scripting languages such as Python or Perl.
Experience debugging designs and simulation environments.
Knowledge of verification principles, testbenches, UVM, and coverage.
Experience working on Artificial Intelligence (AI) / Machine Learning (ML) SoCs.
Working knowledge of writing assertions, coverage, and formal verification.

Responsibilities

Deliver premium-quality silicon designs.
Develop custom intellectual property and System-on-Chip designs.
Build efficient solutions for complex, high-performance functions.
Contribute to digital logic design for AI components, focusing on microarchitecture-based functions and features.
Own logic design and Register Transfer Level (RTL) implementation for high-performance digital IP.
Drive design quality across lint, clock domain crossing (CDC), reset domain crossing (RDC), power, and related design requirements.
Support timing closure and optimization of high-performance digital IP.
Collaborate with verification teams to ensure implementations meet architectural and microarchitectural intent.
Partner with Physical Design (PD), Design for Test (DFT), and other engineering teams to evaluate and optimize design tradeoffs.
Provide technical leadership through mentorship, collaboration, and teamwork.