Principal Design Engineer

Microsoft•Raleigh, NC
•$142,800 - $304,200

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) develops the infrastructure and foundational technologies that support Microsoft's online businesses and Azure platform. The Artificial Intelligence System on Chip (AISoC) team helps define and deliver operational measures of success for hardware manufacturing, improving planning, quality, delivery, scale, and sustainability for Microsoft cloud hardware. The Principal Design Engineer will develop custom intellectual property and System-on-Chip designs, contributing to digital logic design for AI components. The role focuses on microarchitecture-based functions and features, high-performance digital IP, and efficient implementations. It includes ownership of logic design and RTL implementation, driving design quality and supporting timing closure. The engineer will collaborate with verification, physical design, design-for-test, and other teams, and provide technical leadership through mentorship and teamwork.

Requirements

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 3+ years of technical engineering experience; or a master's degree in one of these fields and 6+ years of technical engineering experience; or a bachelor's degree in one of these fields and 8+ years of technical engineering experience; or equivalent experience.
  • Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
  • Must provide proof of citizenship, U.S. residency, or other protected status to assess eligibility for access to export-controlled information; citizenship or status will be verified with appropriate documents.
  • 15+ years of experience in logic design delivering complex solutions.
  • 10+ years of experience in one or more of floating-point arithmetic and datapath design, DMA design, subsystem design/integration, or custom logic design.
  • 5+ years of experience leading logic design teams.
  • Multiple successful ASIC tape-outs in deep sub-micron technologies.
  • Experience with scripting languages such as Python or Perl.
  • Experience debugging designs and simulation environments.
  • Knowledge of verification principles, testbenches, UVM, and coverage.
  • Working knowledge of writing assertions, coverage, and formal verification.

Nice To Haves

  • Experience working on Artificial Intelligence (AI) or Machine Learning (ML) SoCs.

Responsibilities

  • Deliver premium-quality silicon designs.
  • Develop custom intellectual property (IP) and System-on-Chip (SoC) designs.
  • Build efficient solutions for complex, high-performance functions.
  • Contribute to digital logic design for AI components, focusing on microarchitecture-based functions and features.
  • Own logic design and Register Transfer Level (RTL) implementation for high-performance digital IP.
  • Drive design quality across lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), power, and related design requirements.
  • Support timing closure and optimization of high-performance digital IP.
  • Collaborate with verification teams to ensure implementations meet architectural and microarchitectural intent.
  • Partner with Physical Design (PD), Design for Test (DFT), and other engineering teams to evaluate and optimize design tradeoffs.
  • Provide technical leadership through mentorship, collaboration, and teamwork.
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