Principal Design Engineer

Astera Labs•San Jose, CA
•$185,000 - $240,000

About The Position

Astera Labs is seeking Principal Design Engineers to develop micro-architecture and implement front-end circuit design for high-performance network controllers. The work includes RTL, synthesis, IP integration, and block-level verification. Candidates should have knowledge of communication and interface protocols such as PCI Express (Gen 3 and above), UALink, ESUN, and Ethernet. The role involves owning full-chip or block-level designs from architecture through GDS and driving complex designs into production. Engineers will work with digital design tools and flows, contribute to design-for-test and verification activities, and support silicon bring-up and debug. The position requires a professional, customer-minded approach, the ability to manage multiple priorities with minimal supervision, and an entrepreneurial, can-do attitude. Applicants must be authorized to work in the United States and able to start immediately.

Requirements

  • Bachelor’s degree in Electrical Engineering.
  • More than 8 years of experience supporting or developing complex SoC or silicon products for switch ASIC, networking, server, or storage applications.
  • Hands-on, thorough knowledge of high-speed protocols such as PCIe, UALink, ESUN, and Ethernet.
  • Proven front-end design expertise in architecture, RTL, simulation, synthesis, timing closure, GLS, and DFT.
  • Experience owning full-chip or block-level designs from architecture to GDS and driving multiple complex designs to production.
  • Experience with Synopsys and/or Cadence digital design tools and flows.
  • Good knowledge of DFT, including stuck-at and transition scan test insertion.
  • Familiarity with UVM-based design verification.
  • Silicon bring-up and debug expertise.
  • Experience with small-geometry CMOS designs at 28 nm or smaller.
  • Professional attitude, ability to prioritize multiple tasks, and ability to work with minimal guidance and supervision.
  • Entrepreneurial, open-minded, can-do attitude with a customer-focused approach.
  • Authorized to work in the United States and able to start immediately.

Nice To Haves

  • Master’s degree in Electrical Engineering.
  • Firmware development in C.
  • Scripting experience with Python or equivalent programming languages.
  • Development or support experience for PCIe or Ethernet switch products.

Responsibilities

  • Develop micro-architecture and implement front-end circuit design for high-performance network controllers.
  • Perform RTL design, synthesis, IP integration, and block-level verification.
  • Own full-chip or block-level designs from architecture through GDS and drive complex designs to production.
  • Work with high-speed communication and interface protocols, including PCIe, UALink, ESUN, and Ethernet.
  • Contribute to design-for-test activities, including scan test insertion.
  • Support silicon bring-up and debug.
  • Prioritize multiple tasks, prepare for customer meetings, and work with minimal guidance and supervision.
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