Physical Design Engineer

Apple • Cupertino, CA

2d

About The Position

Apple Inc. is hiring a Physical Design Engineer to work in Cupertino, California, and various unanticipated locations throughout the United States. The role partners with logic design teams to understand partition architecture and drive physical design early in the design cycle. It includes implementing partition-level and full-chip physical design, closing timing and physical verification, and meeting schedule and design goals. The engineer also collaborates with CAD and cross-functional teams to improve physical design tools, flows, methodologies, and power, performance, and area (PPA). The position is 40 hours per week.

Requirements

• Bachelor’s degree or foreign equivalent in Electronic Engineering, Electrical Engineering, Computer Engineering, or a related field.
• Five years of progressive, post-baccalaureate experience in the job offered or a related occupation.
• Experience using Cadence Innovus and Synopsys ICC-2 for Place and Route of complex digital logic blocks.
• Experience using PrimeTime-SI to analyze timing results and generate required fixes.
• Ability to use Calibre to understand and debug physical verification results, including LVS, DRC, and antenna checks.
• Understanding of UPF and knowledge of Conformal-LP for verifying low-power intent.
• Experience using Voltus and Redhawk to generate EM and IR results, analyze power-grid integrity, and generate fixes for reported violations.
• Knowledge of TCL, Python, and TCSH for developing automation scripts that improve efficiency.
• Experience using Innovus CCOPT to analyze and optimize clock trees to minimize power and improve latency and skew.

Responsibilities

• Work with the logic design team to understand partition architecture and drive physical design aspects early in the design cycle.
• Conduct floor planning, pin assignments, macro placement, logic evaluation, and placement iterations to optimize placement.
• Perform clock tree synthesis, optimization, routing, and post-route optimization.
• Complete netlist-to-GDS2 implementation for partitions while meeting schedule and design goals.
• Perform setup, hold, transition, and other static timing checks, and complete Static Timing Analysis (STA).
• Run Static IR (voltage drop) and Dynamic IVD (voltage drop) analyses and other power-related optimization and signoff.
• Handle formal checking and signoff, full-chip timing closure, physical verification and closure, and signoff checklist closure.
• Partner with CAD teams to develop tools and methodologies that improve physical design productivity and efficiency.
• Evaluate or develop physical-design-centric flows and methodologies to improve leakage and dynamic power, area, and performance (PPA).
• Work on top-level full-chip Place & Route implementation, complex IP-level partitions, block tiling, feed-through planning, and pin assignment.
• Collaborate with partition-level designers and cross-functional teams to identify the best design solution.

Benefits

• Comprehensive medical and dental coverage.
• Retirement benefits.
• Discounted products and free services.
• Reimbursement for certain educational expenses, including tuition, for formal education related to advancing a career at Apple.
• Potential eligibility for discretionary bonuses or commission payments and relocation.
• Opportunity to participate in discretionary employee stock programs, including restricted stock unit awards and the Employee Stock Purchase Plan.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior