Physical Design Engineer

Apple • Beaverton, OR

2d • Onsite

About The Position

Apple Inc. is hiring a Physical Design Engineer in Beaverton, Oregon. The role implements physical design for partitions and top-level designs, and develops and tests place-and-route flows. It covers floor planning, pin assignments, macro placement, logic evaluation, and iterative placement optimization for timing. The engineer performs clock tree synthesis, optimization, routing, and post-route optimization; conducts static timing checks and closure; and performs power-related analysis and optimization, formal checking, physical verification, and signoff activities. The position is 40 hours per week.

Requirements

• Bachelor’s degree or foreign equivalent in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related field.
• Experience and/or education using Cadence Innovus and Synopsys ICC-2 for place and route of complex digital logic blocks.
• Experience and/or education using PrimeTime-SI to analyze timing results and generate fixes.
• Experience and/or education using Calibre to understand and debug physical verification results, including LVS, DRC, and antenna checks.
• Experience and/or education utilizing UPF and knowledge of Conformal-LP to verify low-power intent.
• Experience and/or education using Voltus and Redhawk to generate and analyze EM and IR results for power-grid integrity.
• Ability to generate fixes based on reported violations.
• Experience and/or education utilizing TCL, Python, and TCSH to develop efficiency-improving automation scripts.
• Experience and/or education using Innovus CCOPT to analyze and optimize clock trees to minimize power and improve latency and skew.
• Ability to leverage semiconductor device physics to make informed power, performance, and area (PPA) trade-offs in place-and-route implementations.
• Experience and/or education using Verilog for design and verification, including the ability to write Verilog modules.
• Knowledge of microprocessor system design, including architecture, datapath, control logic, and memory hierarchy.

Responsibilities

• Implement physical design of partitions and top-level designs.
• Develop and test place-and-route flows.
• Conduct floor planning, pin assignments, macro placement, and logic evaluation.
• Iterate on placement to optimize placement and timing.
• Perform clock tree synthesis, optimization, routing, and post-route optimization.
• Conduct setup, hold, transition, and other static timing checks and closure.
• Run static and dynamic voltage droop analysis and other power-related optimization and signoff.
• Conduct formal checking and signoff, full-chip timing closure, physical verification and closure, and signoff checklist closure.
• Analyze reported violations and generate fixes.

What This Job Offers

• Job Type: Full-time