Physical Design Engineer

Apple • Cupertino, CA

1d

About The Position

Apple Inc. is hiring a Physical Design Engineer in Cupertino, California, and various unanticipated locations throughout the United States. The role works with logic design teams to understand partition architecture and address physical design considerations early in the design cycle. The engineer completes netlist-to-GDS2 implementation for partitions, meeting schedule and design goals, and is responsible for timing, physical and electrical verification, and signoff closure.

The engineer resolves physical-design and flow issues, coordinates place-and-route work, establishes goals and milestones, plans work across short- and long-term horizons, and manages dependencies among top-level design, STA, and block place-and-route domains. The role also advances physical-design methodologies and best-known methods, develops guidelines and checklists, and tracks execution.

Responsibilities span frontend and backend implementation from RTL to GDS2, including synthesis, formal verification (FV), floor planning, netlisting, timing constraints, timing and power convergence, and ECO implementation. The engineer drives timing closure using physical synthesis and place-and-route tools, works with ASIC vendors, and performs hands-on physical implementation and timing closure for core platforms and SoCs. The work includes improving timing signoff criteria, analysis methodologies and flows, and ECO-generation scripts, as well as floor planning and closure for large complex designs with clock cycles above 1 GHz and timing convergence for high-frequency, low-power designs at block, cluster, or full-chip level.

Requirements

• Master’s degree or foreign equivalent in Electrical Engineering, Electrical and Computer Engineering, or a related field.
• Experience and/or education using place-and-route tools such as ICC, ICC2, or Innovus for floor planning, placement, clock optimization, routing, and timing and power optimization for SoC partitions.
• End-to-end understanding of digital design implementation fundamentals, logic modeling, and hardware description languages used in digital IC design.
• Experience using TCL, Perl, Python, and Unix scripting to summarize data, improve execution efficiency, and implement custom scripts that aid partition closure.
• Understanding of physical-design construction and analysis flows and methodologies to execute, close, and sign off SoC partitions.
• Understanding of transistors and digital circuits to make implementation, closure, and signoff trade-offs that meet requirements.
• Understanding of digital logic and computer-architecture fundamentals relevant to IC partitioning and resource planning.
• Ability to interpret results from physical-verification tools such as Calibre and generate fixes for violations.
• Knowledge of signal behavior, interference effects, and noise-reduction principles relevant to high-speed digital circuits.

Responsibilities

• Work with logic design teams to understand partition architecture and address physical-design considerations early in the design cycle.
• Complete netlist-to-GDS2 implementation for partitions while meeting schedule and design goals.
• Own timing, physical and electrical verification, and signoff closure for partitions.
• Resolve physical-design and flow issues, identify potential solutions, and drive their execution.
• Coordinate place-and-route work, set goals and milestones, plan short- and long-term work, and manage dependencies across top-level design, STA, and block place-and-route domains.
• Advance physical-design methodologies and best-known methods; develop guidelines and checklists, drive execution, and track progress.
• Drive timing closure through physical synthesis and place-and-route tools, working with ASIC vendors.
• Drive frontend and backend implementation from RTL to GDS2, including synthesis, FV, floor planning, netlisting, timing constraints, timing and power convergence, and ECO implementation.
• Perform hands-on physical implementation and timing closure for core platforms and SoCs.
• Improve timing signoff criteria, timing-analysis methodologies and flows, and ECO-generation scripts for timing closure.
• Perform floor planning, physical synthesis, and physical-design closure for large complex designs with clock cycles above 1 GHz.
• Drive physical-design and timing convergence for high-frequency, low-power designs at block, cluster, and/or full-chip level.

Benefits

• Comprehensive medical and dental coverage.
• Retirement benefits.
• Discounted products and free services.
• Reimbursement for certain educational expenses, including tuition, for formal education related to advancing a career at Apple.
• Potential eligibility for discretionary bonuses or commission payments.
• Potential relocation assistance.
• Opportunity to participate in discretionary restricted stock unit awards.
• Opportunity to purchase Apple stock at a discount through the Employee Stock Purchase Plan, subject to eligibility and plan terms.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level