Physical Design Engineer

Apple • Cupertino, CA

2d

About The Position

Apple Inc. is hiring a Physical Design Engineer to implement and close physical design partitions for SoCs and core platforms. The role works with logic design and physical design teams to understand partition architecture, drive physical design early in the design cycle, and complete netlist-to-GDS2 implementation within schedule and design goals. It owns timing, physical, and electrical verification and signoff closure, and resolves physical design and flow issues by identifying and implementing solutions.

The engineer serves as a focal point for place-and-route work, coordinating engineers, milestones, dependencies, and short- and long-term plans across domains such as top-level design, STA, and block place and route. The role also drives physical design methodologies and best-known methods, creates guidelines and checklists, tracks execution, and works with ASIC vendors to achieve timing closure.

The position involves frontend and backend implementation from RTL to GDS2, including synthesis, formal verification, floor planning, netlisting, timing constraints, timing and power convergence, and ECO implementation. It includes hands-on physical implementation and timing closure; timing signoff and analysis methodologies; ECO script development; and floor planning and physical design closure for large, complex designs operating at 1 GHz or higher. The engineer drives high-frequency, low-power timing and physical design convergence at block, cluster, and/or full-chip level. The position is based in Cupertino, California, and various unanticipated locations throughout the United States, and is 40 hours per week.

Requirements

• Master’s degree or foreign equivalent in Electrical Engineering, Electrical and Computer Engineering, or a related field.
• At least 2 years of experience in the job offered or a related occupation.
• Experience or education using PNR tools such as ICC, ICC2, or Innovus for place and route, including floor planning, placement, clock optimization, routing, and timing and power optimization for SoC partitions.
• Experience or education using timing analysis tools such as Synopsys PrimeTime for timing analysis and timing ECO generation to close SoC partitions.
• Experience or education using TCL, Perl, or Python and Unix scripting to summarize data, improve execution efficiency, and implement custom scripts that aid partition closure.
• Understanding of physical design construction and analysis flows and methodologies to execute, close, and sign off SoC partitions.
• Understanding of transistors and digital circuits to meet requirements and make appropriate implementation, closure, and signoff trade-offs.
• Ability to interpret EMIR analysis results from tools such as Voltus or Redhawk and generate fixes for violations or to improve QoR.
• Ability to interpret physical verification results from tools such as Calibre and generate fixes for violations.
• Ability to interpret results from LEC and low-power verification tools such as Conformal, Formality, VCLP, and CLP, and make fixes to address violations.

Responsibilities

• Work with the logic design team to understand partition architecture and drive physical design aspects early in the design cycle.
• Complete netlist-to-GDS2 implementation for partitions according to schedule and design goals.
• Own timing, physical, and electrical verification, and drive signoff closure for partitions.
• Resolve physical design and flow issues by identifying potential solutions and driving their execution.
• Coordinate place-and-route work, including setting goals and milestones, planning short- and long-term work, and understanding dependencies across top-level design, STA, and block place-and-route domains.
• Drive physical design methodologies and best-known methods, develop guidelines and checklists, and track execution progress.
• Drive timing closure through physical synthesis and place-and-route tools, working with ASIC vendors.
• Drive frontend and backend implementation from RTL to GDS2, including synthesis, formal verification, floor planning, netlisting, timing constraints, timing and power convergence, and ECO implementation.
• Perform hands-on physical implementation and timing closure for core platforms and SoCs.
• Improve timing signoff criteria, timing analysis methodologies, and flows, and develop or enhance ECO generation scripts for timing closure.
• Perform floor planning, physical synthesis, and physical design closure for large, complex designs with clock cycles at 1 GHz or higher.
• Drive high-frequency, low-power physical design and timing convergence at block, cluster, and/or full-chip level.

Benefits

• Opportunity to participate in discretionary employee stock programs, including restricted stock unit awards and discounted Apple stock through the Employee Stock Purchase Plan, subject to eligibility and program terms.
• Comprehensive medical and dental coverage.
• Retirement benefits.
• Discounted products and free services.
• Reimbursement for certain educational expenses, including tuition, for formal education related to career advancement at Apple.
• Potential eligibility for discretionary bonuses or commission payments.
• Potential relocation assistance.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level