Physical Design Engineer, ML4PD
About The Position
Tenstorrent is seeking a Physical Design Engineer to contribute to the physical design of high-performance chips for AI/ML architectures, with implementation work spanning synthesis through tapeout. The engineer will partner with front-end and physical design engineers to optimize floorplanning, timing, power, performance, and area across multiple IPs, while developing end-to-end ASIC expertise and learning from experienced engineers throughout the chip development process. The role is hybrid and based in Austin, Texas; Fort Collins, Colorado; or Santa Clara, California. Candidates at various experience levels are welcome; interview assessments determine the appropriate level, and the offer will align with that level, which may differ from the level in the posting. The position requires access to technology subject to U.S. export controls. Employment is contingent on eligibility to access that technology, which may depend on citizenship or permanent residency status or the ability to obtain prior license approval. If employment is not possible under U.S. export laws, an offer will be rescinded. Compensation ranges from $100,000 to $500,000, including base and variable compensation targets; the actual offer depends on experience, skills, education, background, and location.
Requirements
- Bachelor’s, master’s, or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Strong logic design fundamentals.
- Experience with synthesis, place-and-route flows, and physical design tools.
- Familiarity with timing, EM/IR, and power analysis.
- Ability to contribute across floorplanning, clocking, I/O planning, timing closure, area improvement, and power optimization.
- Strong Tcl, Perl, Shell, and/or Python skills.
- Knowledge of low-power techniques such as power gating, multi-Vt, and voltage scaling.
Responsibilities
- Contribute to physical design implementation of high-performance AI/ML chips, from synthesis through tapeout.
- Collaborate with front-end and physical design engineers across multiple IPs.
- Optimize floorplanning, timing, power, performance, and area.
- Contribute to clocking, I/O planning, timing closure, area improvement, and power optimization.
- Develop and use flows and experiments to optimize power, performance, and area.
Benefits
- Highly competitive compensation package and benefits
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What This Job Offers
Job Type
Full-time
