Physical Design Engineer

Apple • Cupertino, CA

3d • $174,149 - $225,300

About The Position

Apple Inc. is hiring a Physical Design Engineer to work in Cupertino, California, and various unanticipated locations throughout the USA. The role collaborates with logic design and architecture teams to understand partition architecture, address physical design considerations early, and define, analyze, and document micro-architecture specifications for hardware design blocks. The engineer manages the netlist-to-GDSII implementation process for design partitions and drives timing analysis, physical and electrical verification, and signoff closure. The role also evaluates proposed architectures and algorithms for performance, area, timing, power consumption, complexity, and implementation effort; resolves physical design and flow issues; and optimizes place-and-route partitions for power, performance, and area. The schedule is 40 hours per week. The stated base pay range is $174,149–$225,300 per year, with pay dependent on skills, qualifications, experience, and location.

Requirements

• Master’s degree or foreign equivalent in Electrical and Computer Engineering or a related field.
• Experience and/or education using physical design concepts, construction, analysis flows, and methodology to design SoC ASICs.
• Experience and/or education utilizing Cadence or Synopsys EDA tools to perform automatic place and route on partitions.
• Experience and/or education optimizing logic placement and routing for area, power, and performance, including custom placement and routing using Cadence or Synopsys EDA tools.
• Experience and/or education using floorplanning, I/O placement, and macro placement to achieve high-density layout design.
• Experience and/or education understanding and implementing clocking for designs using Cadence or Synopsys EDA tools.
• Experience and/or education analyzing and ensuring design closure for static timing analysis using tools such as Synopsys PrimeTime or Cadence Innovus/Tempus.
• Experience and/or education leveraging physical design verification tools such as Calibre for layout updates to ensure designs meet DRC/LVS requirements.

Responsibilities

• Collaborate with the logic design team to understand partition architecture and address physical design aspects early in the development cycle.
• Manage the complete netlist-to-GDSII implementation process for design partitions, meeting project schedules and design objectives.
• Perform timing analysis, physical and electrical verification, and drive signoff closure for partitions.
• Work with the architecture team to define, analyze, and document micro-architecture specifications of hardware design blocks.
• Conduct feasibility analyses of proposed architectures and algorithms, assessing performance, area, timing, power consumption, complexity, and implementation effort.
• Resolve and improve physical design and flow issues, identify potential solutions, and drive execution.
• Optimize place-and-route partitions to achieve the best power, performance, and area.

What This Job Offers

• Job Type: Full-time