Physical Design Engineer

Apple•Cupertino, CA

About The Position

Apple Inc. is hiring a Physical Design Engineer in Cupertino, California, and various unanticipated locations throughout the USA. The engineer collaborates with logic design teams to understand partition architecture and address physical-design considerations early in development. The role manages the complete netlist-to-GDSII implementation process for design partitions, meeting project schedules and design objectives, and is responsible for timing analysis, physical and electrical verification, and signoff closure. The engineer works with architecture teams to define, analyze, and document micro-architecture specifications for hardware design blocks. The role also evaluates proposed architectures and algorithms for performance, area, timing, power consumption, complexity, and implementation effort; resolves and improves physical-design and flow issues; and optimizes place-and-route partitions for power, performance, and area. The position is 40 hours per week.

Requirements

Master’s degree or foreign equivalent in Electrical and Computer Engineering or a related field.
Experience and/or education using physical-design concepts, construction, analysis flows, and methodology to design SoC ASICs.
Experience and/or education using Cadence or Synopsys EDA tools to perform automatic place and route on partitions.
Experience and/or education optimizing logic placement and routing for area, power, and performance, including custom placement and routing using Cadence or Synopsys EDA tools.
Experience and/or education using floorplanning, I/O placement, and macro placement to achieve high-density layout design.
Experience and/or education understanding and implementing clocking for designs using Cadence or Synopsys EDA tools.
Experience and/or education analyzing and ensuring design closure for static timing analysis using tools such as Synopsys PrimeTime or Cadence Innovus/Tempus.
Experience and/or education using physical-design verification tools such as Calibre for layout updates to ensure designs meet DRC/LVS requirements.

Responsibilities

Collaborate with logic design teams to understand partition architecture and address physical-design aspects early in the development cycle.
Manage the netlist-to-GDSII implementation process for design partitions, ensuring project schedules and design objectives are met.
Perform timing analysis, physical and electrical verification, and drive signoff closure for partitions.
Work with architecture teams to define, analyze, and document micro-architecture specifications for hardware design blocks.
Conduct feasibility analyses of proposed architectures and algorithms, evaluating performance, area, timing, power consumption, complexity, and implementation effort.
Resolve and improve physical-design and flow issues, identify potential solutions, and drive execution.
Optimize place-and-route partitions to achieve the best power, performance, and area.