Physical Design Engineer

Apple • Austin, TX

2d • Onsite

About The Position

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Work on graphics projects from start to end for clock implementation which involve multiple clock domains. Work on clock architecture and designing high speed clock distribution circuits; Responsible for clock planning, building simulation models (Using Spice), & interacting with Floorplan owner to understand any Power domain/routing/placement challenges for the clocking. Involve in Clock repeater studies for a certain process technology with different size buffer, fanout, metal spec studies were done (Using Spice) and tabulated in excel for implementation engineer to choose right cell and layer based on nature of clock; and Involving in Clock cell definition and sizes and family of custom clock cell needed for a particular process technology. 40 hours/week.

Requirements

• Master’s degree or foreign equivalent in Electrical and Computer Engineering or related field
• 1 year of experience in the job offered or related occupation
• 1 year of experience with building high-speed clock distribution networks optimized for performance and reliability
• 1 year of experience implementing designs across multiple clock domains with proper synchronization and isolation
• 1 year of experience executing clock planning with considerations for power domains, routing congestion, and placement constraints
• 1 year of experience optimizing clock trees to minimize latency and skew for high-performance designs
• 1 year of experience analyzing and selecting clock repeater and buffer configurations across various process technologies
• 1 year of experience tuning metal layer usage and fanout strategies to enhance clock signal integrity and timing
• 1 year of experience debugging physical design verification (PDV) issues such as DRC, LVS, shorts, and opens during clock construction
• Experience with Spice simulations
• Experience with Excel tabulation

Responsibilities

• Work on graphics projects from start to end for clock implementation which involve multiple clock domains.
• Work on clock architecture and designing high speed clock distribution circuits.
• Responsible for clock planning, building simulation models (Using Spice), & interacting with Floorplan owner to understand any Power domain/routing/placement challenges for the clocking.
• Involve in Clock repeater studies for a certain process technology with different size buffer, fanout, metal spec studies were done (Using Spice) and tabulated in excel for implementation engineer to choose right cell and layer based on nature of clock.
• Involving in Clock cell definition and sizes and family of custom clock cell needed for a particular process technology.
• Build high-speed clock distribution networks optimized for performance and reliability.
• Implement designs across multiple clock domains with proper synchronization and isolation.
• Execute clock planning with considerations for power domains, routing congestion, and placement constraints.
• Optimize clock trees to minimize latency and skew for high-performance designs.
• Analyze and select clock repeater and buffer configurations across various process technologies.
• Tune metal layer usage and fanout strategies to enhance clock signal integrity and timing.
• Debug physical design verification (PDV) issues such as DRC, LVS, shorts, and opens during clock construction.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level