Physical Design Engineer

Apple • Beaverton, TX

2d

About The Position

Apple is seeking a forward-thinking Physical Design Engineer to contribute to the design of high-performance PHYs. The role works with architecture, CAD, timing, and logic design teams and spans all phases of physical design, from RTL through final GDSII delivery. The engineer will develop physical designs that meet timing, area, and power constraints, support chip integration, and help establish physical design methodologies.

Requirements

• Bachelor of Science in Electrical Engineering and at least 10 years of relevant industry experience, or equivalent.
• Deep design experience in high-performance PHY and/or SoC designs is sought for the ideal candidate.
• Deep knowledge of physical design industry standards and practices, including physically aware synthesis, floorplanning, and place and route.
• Experience developing and implementing power-grid and clock specifications.
• Strong understanding of physical construction, integration, and physical verification.
• Knowledge of basic SoC architecture and HDL languages such as Verilog to work with the logic design team on timing fixes.
• Proficiency with industry-standard physical design and synthesis tools.
• Deep understanding of scripting languages such as Perl and Tcl.
• Solid understanding of extraction and static timing analysis (STA) methodology and tools.
• Deep understanding of physical design verification methodology and debugging LVS/DRC issues at chip and block level.

Responsibilities

• Generate block- and chip-level static timing constraints.
• Build full-chip floorplans, including pin placement, partitions, and power grids.
• Develop and validate guidelines for high-performance, low-power clock networks.
• Perform block-level place and route and close designs to meet timing, area, and power constraints.
• Generate and implement ECOs to address timing, noise, and EM/IR violations.
• Run chip- and block-level physical design verification and provide other designers with guidelines for fixing LVS/DRC violations.
• Participate in establishing CAD and physical design methodologies for correct-by-construction designs.
• Assist in developing chip-integration flows.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior