Physical Design Engineer

Apple • Cupertino, CA

3d • $150,400 - $225,300

About The Position

Apple Inc. is hiring a Physical Design Engineer in Cupertino, California, and various unanticipated locations throughout the USA. The engineer will contribute to all phases of physical design for high-performance PHY designs, from RTL through delivery of final GDSII. The role includes developing timing constraints, chip floorplans and clock-network guidelines; completing place-and-route and design closure; resolving timing, noise, and EM/IR violations; and supporting physical-design verification, CAD methodologies, and chip-integration flow development. The position is 40 hours per week.

Requirements

• Master's degree or foreign equivalent in Electrical Engineering or a related field.
• Experience and/or education identifying root-cause LVS, DRC, and ERC issues and closing PDV to avoid manufacturing and silicon-reliability issues.
• Experience and/or education using Tcl, Perl, and Python scripting for physical-design data mining and flow customization.
• Experience and/or education collecting PPA data, demonstrating power-performance tradeoffs, and identifying optimal solutions for specific designs.
• Experience and/or education using low-power techniques such as clock gating and power gating to reduce leakage and dynamic power.
• Experience and/or education using EMIR analysis to understand hotspot violations and fixes.
• Experience and/or education using ML algorithms and models for data mining and improving design quality and performance.
• Experience and/or education in design, simulation, and layout generation using industry-standard tools such as Cadence or Virtuoso.

Responsibilities

• Contribute to all phases of physical design for high-performance PHY designs, from RTL to final GDSII delivery.
• Generate block- and chip-level static timing constraints.
• Build full-chip floorplans, including pin placement, partitions, and power grids.
• Develop and validate high-performance, low-power clock-network guidelines.
• Perform block-level place and route and close designs to meet timing, area, and power constraints.
• Generate and implement ECOs to fix timing, noise, and EM/IR violations.
• Run chip- and block-level physical-design verification and provide guidelines to designers for fixing LVS/DRC violations.
• Participate in establishing CAD and physical-design methodologies for correct-by-construction designs.
• Assist in developing chip-integration flows.

Benefits

• Opportunity to participate in discretionary employee stock programs, including discretionary restricted stock unit awards and discounted stock purchases through the Employee Stock Purchase Plan.
• Comprehensive medical and dental coverage.
• Retirement benefits.
• Discounted products and free services.
• Reimbursement for certain education expenses, including tuition, for formal education related to advancing a career at Apple.
• The role might be eligible for discretionary bonuses or commission payments.
• The role might be eligible for relocation.

What This Job Offers

• Job Type: Full-time