Physical Design Engineer

Ambarella•Headquarters, KY

6d•$140,000 - $156,000

About The Position

The Physical Design Engineer will be an integral part of the physical design team, performing physical design implementation and verification for Ambarella’s low-power AI SoC from netlist to GDSII. The role spans all phases of SoC implementation and may cover work at the block and/or full-chip level.

Requirements

BS/MS in electrical engineering or computer science, or equivalent experience.
3–5+ years of experience.
Good understanding of VLSI digital design, layout, and timing closure.
Basic knowledge of circuit design, device delays, and gate-level timing.
Familiarity with industry EDA tools, such as Cadence Innovus, Quantus, and Tempus; Synopsys Fusion Compiler, ICC2, StarRC, and PrimeTime; and Mentor Calibre.
Proficient programming and scripting skills in Perl, Python, TCL, C-shell, and make.
Knowledge of hardware description languages such as Verilog and VHDL.
Self-motivated team worker with good verbal and written interpersonal skills.
Solid understanding of hierarchical physical design strategies and methodologies, as well as nanometer advanced-node technology issues.
Hands-on STA experience, including multi-mode, multi-corner analysis, and ability to analyze and fix critical timing issues.

Nice To Haves

Experience with Cadence Innovus, Genus, and Conformal, and Synopsys PrimeTime and StarRC.
Proven track record of delivering tape-out-quality GDSII with silicon success in sub-10 nm.

Responsibilities

Perform floor-planning and automatic place and route.
Conduct static timing analysis and implement engineering change orders (ECOs).
Perform signal integrity and EM/IR analysis.
Conduct formal verification and physical layout verification, including LVS, DRC, and DFM.