Physical Design Engineer

Apple•Cupertino, CA

1d•$150,400 - $225,300

About The Position

Apple Inc. is hiring a Physical Design Engineer in Cupertino, California, and various unanticipated locations throughout the USA. The engineer will contribute to all phases of the physical design of high-performance PHY designs, from RTL through delivery of final GDSII. The role includes developing timing constraints, creating floor plans, implementing clock networks, and completing place-and-route while meeting timing, area, and power constraints. The position also supports physical design verification, CAD and physical design methodology development, and chip integration flow development. The schedule is 40 hours per week. The stated base pay range is $150,400–$225,300 per year. Base pay depends on skills, qualifications, experience, and location. Apple employees may be eligible for discretionary stock awards and an employee stock purchase plan, comprehensive medical and dental coverage, retirement benefits, discounted products and free services, and reimbursement for certain education expenses, including tuition. The role may also be eligible for discretionary bonuses or commission payments and relocation, subject to applicable eligibility requirements and plan terms.

Requirements

Master’s degree or foreign equivalent in Electrical Engineering or a related field.
Experience and/or education identifying root-cause LVS, DRC, and ERC issues and closing PDV to avoid manufacturing and silicon reliability issues.
Experience and/or education using Tcl, Perl, and Python scripting for physical design data mining and flow customization.
Experience and/or education collecting PPA (power/performance/area) data, demonstrating power-performance tradeoffs, and determining an optimal solution for a specific design.
Experience and/or education using low-power techniques such as clock gating and power gating to reduce leakage and dynamic power.
Experience and/or education using EMIR analysis to understand and address hotspot violations.
Experience and/or education using machine-learning algorithms and models for data mining and improving design quality and performance.
Experience and/or education with design, simulation, and layout generation using industry-standard tools such as Cadence or Virtuoso.

Responsibilities

Contribute to all phases of physical design for high-performance PHY designs, from RTL to delivery of final GDSII.
Generate block- and chip-level static timing constraints.
Build full-chip floor plans, including pin placement, partitions, and power grids.
Develop and validate guidelines for high-performance, low-power clock networks.
Perform block-level place and route and close designs to meet timing, area, and power constraints.
Generate and implement ECOs to fix timing, noise, and EMIR violations.
Run chip- and block-level physical design verification and provide guidelines to designers for fixing LVS/DRC violations.
Participate in establishing CAD and physical design methodologies for correct-by-construction designs.
Assist in developing flows for chip integration.