Physical Design Engineer

Apple • San Diego, CA

3d • $175,000 - $263,300 • Onsite

About The Position

Apple Inc. is hiring a Physical Design Engineer in San Diego, California. The role focuses on full-chip clock-tree construction and planning, clock specification generation and automation, and netlist-to-GDS2 implementation for design partitions. The engineer will work with logic design teams to understand partition architecture and address physical-design considerations early in the design cycle, while meeting schedule and design goals. The position also involves timing, physical, and electrical verification; signoff closure; and resolving physical-design and flow issues.

The position is 40 hours per week. The stated base pay range is $175,000–$263,300 per year, depending on skills, qualifications, experience, and location. Apple describes benefits including medical and dental coverage, retirement benefits, discounted products and free services, and reimbursement for certain career-related educational expenses, including tuition. Employees may also be eligible for discretionary stock awards, an employee stock purchase plan, discretionary bonuses or commissions, and relocation assistance, subject to applicable eligibility requirements and plan terms.

Requirements

• Master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, or a related field.
• Two years of experience in the job offered or a related occupation.
• Experience building clock networks for high-performance CPU cores and ensuring minimal latency on the latest technologies.
• Experience analyzing interconnect delays, parasitics, and coupling, and understanding their impact on system performance.
• Experience optimizing interconnect wire delays for dynamic power performance.
• Experience with FinFET and GAA standard-cell technologies for physical design targeting performance, power, and area.
• Experience building full-chip clock trees, generating specifications, and planning clocks, including designing and constructing recombinant networks.
• Experience automating clock-tree specification generation for clock construction and distribution across dies to meet clock specifications, latency, and power goals.
• Experience using industry-standard EDA tools, including Synopsys or Cadence, and understanding the algorithms that drive them.
• Experience performing static timing analysis, physical-design verification analysis, and place-and-route methodology to achieve performance, power, and area goals.

Responsibilities

• Build full-chip clock trees and perform clock specification generation and clock planning, including design and construction of recombinant networks.
• Automate clock-tree specification generation for clock construction and distribution across dies, meeting clock specifications, latency, and power goals.
• Work with logic design teams to understand partition architecture and drive physical-design considerations early in the design cycle.
• Complete netlist-to-GDS2 implementation for design partitions while meeting schedule and design goals.
• Conduct timing, physical, and electrical verification and drive signoff closure for partitions.
• Resolve physical-design and flow issues, identify potential solutions, and drive their execution.

Benefits

• Comprehensive medical and dental coverage
• Retirement benefits
• Discounted products and free services
• Reimbursement for certain career-related educational expenses, including tuition
• Discretionary restricted stock unit awards
• Employee Stock Purchase Plan with discounted Apple stock
• May be eligible for discretionary bonuses or commission payments
• May be eligible for relocation assistance

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level