Physical Design Engineer

Apple • Austin, TX

3d • Onsite

About The Position

Apple Inc. has an opening in Austin, Texas, for an ASIC block-level Physical Design Engineer working on GPU designs. The role covers the physical design process from floor planning through implementation, verification, and analysis. Work includes floor planning, pin assignment, macro and logic placement, clock tree synthesis, routing, timing, physical verification, and electrical analysis. The engineer will apply low-power techniques, perform design rule checks and layout-versus-schematic checks, support static timing analysis and block closure, and analyze and close electromigration and electrical reliability issues. Scripting is used to extract and analyze design data.

The position is 40 hours per week. Apple Inc. requires a Master’s degree or foreign equivalent in Electrical Engineering or a related field, plus two years of experience in the job offered or a related occupation. The required education and experience must include the specified circuit and physical-design concepts, tools, and scripting skills.

Requirements

• Master’s degree or foreign equivalent in Electrical Engineering or a related field.
• At least two years of experience in the job offered or a related occupation.
• Experience using MOS, VLSI circuit design, or computer systems with transistor-level fundamentals and design architecture for physical design work and troubleshooting.
• Experience using Innovus or IC Compiler for block-level floor planning, placement, and routing.
• Experience using PrimeTime for static timing analysis, hierarchical design, top-down design, budgeting, and timing closure.
• Experience using Calibre for physical verification and design rule closure.
• Experience using Voltus for electrical analysis.
• Experience using Genus or DC Compiler and Innovus or IC Compiler to work with RTL teams on floor planning and physical implementation, including early RTL feedback.
• Experience using Innovus or IC Compiler for physical construction and optimization flows to improve performance, power, and area (PPA).
• Experience using Perl, Tcl, or Python to parse physical design reports and logs, create design metrics, and configure tool capabilities.

Responsibilities

• Perform ASIC block-level physical design for GPU designs through floor planning, placement, clock tree synthesis, routing, timing, physical verification, and electrical analysis.
• Perform floor planning, pin assignment, macro placement, logic placement, clock tree synthesis, and routing analysis.
• Apply low-power techniques, including clock gating, power gating, and multi-voltage designs.
• Perform physical verification, including design rule checks (DRC) and layout-versus-schematic (LVS) checks, to verify compliance with fabrication requirements.
• Perform static timing analysis and support block closure to meet timing requirements.
• Perform electromigration and electrical analysis (EMIR) and support closure of related issues.
• Use scripting to extract and analyze design data.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level