Physical Design Engineer

Apple • San Diego, CA

2d

About The Position

Apple Inc. is hiring a Physical Design Engineer in San Diego, California. The role builds full-chip clock trees and generates specifications and clock plans, including the design and construction of recombinant networks. It automates clock-tree specification generation and clock construction and distribution across dies to meet clock specifications for latency and power. The engineer works with the logic design team to understand partition architecture and address physical design early in the design cycle; implements partitions from netlist to GDS2 to meet schedules and design goals; conducts timing, physical, and electrical verification; and drives signoff closure. The role also resolves physical-design and flow issues by identifying potential solutions and driving their execution.

The position is 40 hours per week. The stated base pay range is $175,000–$263,300 per year, with pay depending on skills, qualifications, experience, and location. Apple also describes discretionary stock awards and an employee stock purchase plan, medical and dental coverage, retirement benefits, discounted products and free services, and reimbursement for certain career-related education expenses, including tuition. The role might also be eligible for discretionary bonuses or commission payments and relocation.

Requirements

• Master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, or a related field.
• At least 2 years of experience in the job offered or a related occupation.
• Experience or education building clock networks for high-performance CPU cores and ensuring minimal latency on the latest technologies.
• Experience or education analyzing interconnect delays, parasitics, and coupling, and understanding their impact on system performance.
• Experience or education optimizing interconnect wire delays for optimal dynamic-power performance.
• Experience or education performing physical design with FinFET and GAA standard-cell technologies to achieve performance, power, and area goals.
• Experience or education building full-chip clock trees and performing specification generation and clock planning involving design and construction of recombinant networks.
• Experience or education automating clock-tree specification generation for clock construction and distribution across dies to meet clock specifications, latency, and power goals.
• Experience or education using industry-standard EDA tools, including Synopsys or Cadence, and understanding the algorithms driving them.
• Experience or education performing static timing analysis, physical-design verification analysis, and place-and-route methodology to achieve PPA goals.

Responsibilities

• Build full-chip clock trees and perform specification generation and clock planning, including design and construction of recombinant networks.
• Automate clock-tree specification generation for clock construction and distribution across dies to meet clock specifications for latency and power.
• Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle.
• Complete netlist-to-GDS2 implementation for partitions, meeting schedule and design goals.
• Conduct timing, physical, and electrical verification, and drive signoff closure for partitions.
• Resolve physical-design and flow issues, identify potential solutions, and drive execution.

Benefits

• Opportunity to participate in discretionary employee stock programs, including restricted stock unit awards and an employee stock purchase plan with discounted Apple stock.
• Comprehensive medical and dental coverage.
• Retirement benefits.
• Discounted products and free services.
• Reimbursement for certain education expenses, including tuition, for formal education related to career advancement at Apple.
• May be eligible for discretionary bonuses or commission payments.
• May be eligible for relocation.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level