Physical Design CPU Methodology Engineer

Tenstorrent•Santa Clara, CA

7d•Remote

About The Position

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a Physical Design CPU Methodology Engineer who defines and drives the implementation methodology, automation strategy, and signoff infrastructure for high-performance CPU cores across advanced process nodes. This role combines deep physical design expertise with organization-level technical leadership, enabling predictable RTL-to-GDS execution, strong PPA outcomes, and scalable methodology adoption across multiple projects and teams. This role is remote based out of the United States. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Requirements

Experienced Physical Design Engineer with 10+ years of ASIC/SoC/CPU experience, ideally focused on high-performance CPUs or similarly complex digital designs.
Deep expertise across RTL-to-GDS implementation and signoff, including timing closure, power optimization, SI, EM/IR, extraction, and physical verification.
Experience building or owning physical design methodology, automation, or CAD flows.
Highly skilled in Tcl, Python, Perl, or similar scripting languages.
Technical leader who can influence across teams, mentor engineers, and drive standards across geographically distributed organizations.

Responsibilities

Define and own scalable CPU physical design methodology spanning synthesis, floorplanning, power planning, place and route, CTS, extraction, STA, SI, EM/IR, and physical verification.
Explore AI/ML-enabled PD tooling, begin synthesis and PnR of CPU partitions, and start developing the new program RM flow.
Drive automation, constraints, quality metrics, signoff criteria, dashboards, checkers, and debug workflows that improve predictability, turnaround time, and PPA.
Partner with architecture, RTL, circuit, DFT, CAD, program, data, and EDA vendor teams to enable advanced nodes and productize AI/ML across physical design.