Physical Design CPU Methodology Engineer

Tenstorrent•Santa Clara, CA

19h•$100,000 - $500,000•Remote

About The Position

Tenstorrent is looking for a Physical Design CPU Methodology Engineer who defines and drives the implementation methodology, automation strategy, and signoff infrastructure for high-performance CPU cores across advanced process nodes. This role combines deep physical design expertise with organization-level technical leadership, enabling predictable RTL-to-GDS execution, strong PPA outcomes, and scalable methodology adoption across multiple projects and teams. This role is remote based out of the United States. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Requirements

Experienced Physical Design Engineer with 10+ years of ASIC/SoC/CPU experience, ideally focused on high-performance CPUs or similarly complex digital designs.
Deep expertise across RTL-to-GDS implementation and signoff, including timing closure, power optimization, SI, EM/IR, extraction, and physical verification.
Experience building or owning physical design methodology, automation, or CAD flows.
Highly skilled in Tcl, Python, Perl, or similar scripting languages.
Technical leader who can influence across teams, mentor engineers, and drive standards across geographically distributed organizations.

Nice To Haves

How to apply AI/ML to physical design for hotspot prediction, congestion forecasting, timing-risk classification, ECO prioritization, IR-drop screening, and flow tuning.
How to build reliable, explainable, production-ready data infrastructure, including feature collection, validation, and signoff integration.
How to evaluate AI-enabled EDA capabilities and determine where data-driven optimization delivers measurable value over conventional heuristics.
How to scale CPU methodology, automation, and AI/ML deployment across advanced-node programs, foundries, teams, and the broader organization.

Responsibilities

Define and own scalable CPU physical design methodology spanning synthesis, floorplanning, power planning, place and route, CTS, extraction, STA, SI, EM/IR, and physical verification.
Explore AI/ML-enabled PD tooling, begin synthesis and PnR of CPU partitions, and start developing the new program RM flow.
Drive automation, constraints, quality metrics, signoff criteria, dashboards, checkers, and debug workflows that improve predictability, turnaround time, and PPA.
Partner with architecture, RTL, circuit, DFT, CAD, program, data, and EDA vendor teams to enable advanced nodes and productize AI/ML across physical design.