Physical Design and CAD Engineer

Astera Labs • San Jose, CA

1d

About The Position

Astera Labs is hiring a Physical Design and CAD Engineer to serve as a technical lead developing next-generation connectivity ASICs for cloud and AI infrastructure. The role combines Physical Design CAD methodology development with hands-on place-and-route implementation. The engineer will develop and optimize automated design flows for advanced process nodes while contributing to block-level physical design, timing closure, and GDSII signoff, collaborating with cross-functional teams to improve design efficiency, automation, and silicon implementation.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• At least 5 years of experience in ASIC Physical Design, CAD methodology, or design automation.
• Strong understanding of physical design implementation and RTL-to-GDSII methodologies.
• Experience developing or maintaining Physical Design CAD flows.
• Hands-on experience with place-and-route, timing closure, and physical design signoff.
• Proficiency in Python and/or Tcl scripting.
• Experience with Cadence and/or Synopsys physical design tools.
• Experience with advanced semiconductor process nodes (7nm or below).

Nice To Haves

• Master's degree.
• Experience with 3nm or more advanced process technologies.
• Experience building automated CAD flows from synthesis through signoff.
• Familiarity with Cadence Innovus, Tempus, and Genus, and Synopsys ICC2, Fusion Compiler, and PrimeTime.
• Experience with EM/IR analysis, DRC/LVS, ECO, and timing signoff methodologies.
• Experience with block-level ownership through tapeout.
• Experience developing scalable CAD methodologies and automation frameworks.

Responsibilities

• Develop and maintain Physical Design CAD flows and methodologies for advanced process nodes.
• Build automation frameworks using Python and Tcl to support the process from synthesis through signoff.
• Perform hands-on physical design and place-and-route, including floorplanning, placement, clock-tree synthesis (CTS), routing, and timing closure.
• Develop and optimize EDA tool flows for timing analysis, extraction, EM/IR, and physical verification.
• Support block-level implementation from synthesis through GDSII signoff.
• Improve design quality, automation, and flow efficiency.
• Collaborate with design, verification, and engineering teams to support ASIC development and tapeout.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior