Experienced Module Integration Engineer
About The Position
Samsung Austin Semiconductor is seeking a Module Integration Engineer for its 2nm GAAFET team. The role focuses on Front-End-of-Line (FEOL) integration, specifically the RPMG (Replacement Metal Gate) and CTSDB (PC and NS isolation) modules. As the company transitions from FinFET to GAAFET architecture, the engineer will help connect unit process development with device performance, working across lithography, etch, deposition, and device physics to integrate gate stack and contact modules for next-generation computing. The engineer will support integration and optimization of the RPMG and CTSDB modules to meet 2nm device specifications, monitor trends, and respond to process-control or optimization issues. The role includes collaboration with unit process, Device, and Layout teams; running and analyzing designed experiments; interpreting metrology and failure-analysis data; and using statistical and programming tools to correlate process parameters with device yield. This is a full-time, on-site position. The base salary range is $95,000–$120,000, with compensation determined by factors including duties, location, education, skills, qualifications, and experience. Total compensation includes a benefits package and may include incentive compensation based on organizational and individual performance.
Requirements
- Master’s degree in Materials Science, Chemistry, Physical Chemistry, Physics, or a closely related field; industry experience may substitute for an advanced degree.
- Knowledge of MOSFET physics, with a deep understanding of device physics, especially interfacial physics such as gate oxide, threshold-voltage control, gate capacitance, performance, and reliability.
- Experience with, or ability to understand, semiconductor processes such as ALD/CVD deposition, etch, and CMP.
- Intermediate proficiency in Python, R, and SQL for automating data extraction and visualization.
- Strong experience with Microsoft Excel and PowerPoint; Excel skills should include basic data-manipulation formulas such as VLOOKUP and MATCH.
- Proficiency in Spotfire, Minitab, or similar statistical software for yield and process analysis.
- Awareness of or experience with workflow styles such as Waterfall and Agile, and software such as Confluence and Jira.
Nice To Haves
- Ph.D. in Materials Science, Chemistry, Physical Chemistry, Physics, or a closely related field.
- Two to three years of relevant experience (preferred, but not required).
- Knowledge of GAAFET device physics; FinFET knowledge is also desired.
Responsibilities
- Support integration and optimization of the RPMG and CTSDB modules to meet target device specifications for the 2nm node.
- Monitor process trends regularly and take responsive action when needed.
- Collaborate with unit process engineers in Etch, CVD, ALD, CMP, and Lithography to address module risks and process-control or optimization issues.
- Execute and analyze Design of Experiments (DOE) to evaluate how process variations affect electrical performance.
- Interpret advanced metrology and analysis data, including TEM, SEM, AFM, and EDX, to identify root causes of module failures and implement corrective actions.
- Use statistical software and programming tools to analyze large datasets and correlate process parameters with device yield.
- Participate in design reviews and synchronization meetings with Device and Layout teams to ensure manufacturability.
Benefits
- Medical insurance
- Dental insurance
- Vision insurance
- Life insurance
- 401(k) matching with immediate vesting
- Onsite cafés and workout facilities
- Paid maternity leave
- Paid paternity leave
- Paid time off
- Two personal holidays and ten regular holidays
- Wellness incentives
- Eligible full-time employees may receive MBO bonuses based on company, division, and individual performance.
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
