Experienced Module Integration Engineer
About The Position
Samsung Austin Semiconductor is seeking a motivated, high-caliber Module Integration Engineer to join its 2nm GAAFET team. The position focuses on Front-End-of-Line (FEOL) integration, specifically the RPMG (Replacement Metal Gate) and CTSDB (PC and NS isolation) modules. As the company transitions from FinFET to GAAFET architecture, the engineer will connect unit process development with overall device performance and support integration of gate stack and contact modules for next-generation computing. The engineer will support and optimize the RPMG and CTSDB modules to meet 2nm device specifications, monitor trends, and respond to issues. The role works across lithography, etch, deposition, and device physics, collaborating with unit process engineers and Device and Layout teams. It involves designing and analyzing experiments, interpreting advanced metrology data, identifying root causes of module failures, and using statistical and programming tools to analyze process data and device yield.
Requirements
- Master’s degree in Materials Science, Chemistry, Physical Chemistry, Physics, or a closely related field; industry experience may substitute for an advanced degree.
- Knowledge of MOSFET physics, particularly device and interfacial physics, including gate oxide, threshold-voltage control, gate capacitance, performance, and reliability.
- Experience with or ability to understand semiconductor processes such as ALD/CVD deposition, etch, and CMP.
- Intermediate proficiency in Python, R, and SQL for automating data extraction and visualization.
- Comfort and experience with Microsoft Excel and PowerPoint; Excel skills should include basic data-manipulation formulas such as VLOOKUP and MATCH.
- Proficiency in Spotfire, Minitab, or similar statistical software for yield and process analysis.
- Awareness or experience with Waterfall and Agile workflow styles and software such as Confluence and Jira.
Nice To Haves
- Ph.D. in Materials Science, Chemistry, Physical Chemistry, Physics, or a closely related field.
- Knowledge of GAAFET device physics; FinFET knowledge is also desired.
- Two to three years of relevant experience is preferred, but not required.
Responsibilities
- Support integration and optimization of the RPMG and CTSDB modules to meet 2nm device specifications.
- Monitor process trends daily and take responsive action when needed.
- Collaborate with Etch, CVD, ALD, CMP, and Lithography unit process engineers on module risks, process control, and optimization.
- Execute and analyze Design of Experiments (DOE) to evaluate the effects of process variations on electrical performance.
- Interpret TEM, SEM, AFM, and EDX metrology and analysis data to identify root causes of module failures and implement corrective actions.
- Use statistical software and data sources to analyze large datasets and correlate process parameters with device yield.
- Participate in design reviews and synchronization meetings with Device and Layout teams to ensure manufacturability.
Benefits
- Medical insurance
- Dental insurance
- Vision insurance
- Life insurance
- 401(k) matching with immediate vesting
- Onsite cafés
- Onsite workout facilities
- Paid maternity leave
- Paid paternity leave
- Paid time off (PTO)
- Two personal holidays and ten regular holidays
- Wellness incentives
- Eligible full-time employees may receive MBO bonuses based on company, division, and individual performance
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
