Memory Architect

Normal Computing Corporation • Palo Alto, CA

20d

About The Position

Normal Computing is seeking a Memory Architect to translate its Thermo In-Memory Computing concepts into silicon for AI inference hardware. The role involves reimagining conventional memory design—including read/write paths, memory-array organization, and microarchitecture—to interleave core memory operations with high-performance compute and pursue substantial AI inference performance improvements.

The Memory Architect reports to the Director of Silicon Engineering and partners with scientists, microarchitects, physical design engineers, and analog design engineers. The role helps implement a standard-cell library combining digital compute primitives with ThermoDRAM compute primitives and translates those primitives into a Compute In-Memory System. The architect also owns technical relationships with major manufacturers, from PDK acquisition through test-chip tapeout and production silicon.

Requirements

• Substantial experience in memory architecture or circuit design at a memory manufacturer or memory-centric compute company.
• Deep understanding of memory-array physics, including SRAM cells (1T/3T/6T/8T), DRAM bitcells, capacitance, sensing, read/write operations, core timing, retention, and reliability.
• Hands-on experience with embedded memory or random-access memory technology and PDKs, including developing memory test chips through tapeout.
• Ability to work across SPICE-level circuit behavior and architecture-level performance and power models.
• Strong fundamentals in at least one programming language, such as Python, C, or C++, for modeling and performance prediction.
• Experience with RTL and SystemVerilog to model and optimize dataflow and specify compute-block requirements.
• Experience with different interface types, including memory interfaces.
• Excellent written and spoken communication skills.

Nice To Haves

• Experience with processing-in-memory or near-memory compute.
• Experience with non-volatile memory technology.
• Experience with DRAM technology, including eDRAM.
• Major publications at ISSCC, VLSI, IEDM, ISCA, or other major conferences.
• Existing relationships with manufacturers.

Responsibilities

• Define processing-in-memory architecture, memory requirements, and floorplans, including novel memory primitives and read/write circuitry and row/column decoders.
• Architect local and global datapaths, segmented buses, and on-die fabrics for moving data between memory arrays and logic.
• Own power distribution, power budgets, thermal limits, redundancy, and ECC to support memory and compute performance while protecting retention and yield.
• Own access to PDKs and design rules, assess architectural modifications against process capabilities, and drive tapeout planning, test-chip content, schedules, and bring-up.
• Partner with analog engineers developing and characterizing the primitive device library, including write circuits, drivers, and multiplexers; set requirements and align design choices with architectural performance needs.
• Define interfaces between the custom memory product and external hosts, including relevant interface types, command-set extensions, and controller and timing implications.
• Oversee SPICE, analytical, and cycle-level models of performance, power, and yield.
• Work with performance and machine-learning engineers to validate that projected PPA improvements translate into workload-level gains.
• Own technical relationships with major manufacturers from PDK acquisition through test-chip tapeout and production silicon.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed