Manager, ASIC Design Engineering (Starshield Satellite Engineering)

SpaceX•Hawthorne, CA

6h•Onsite

About The Position

The Manager, ASIC Design Engineering will lead a team that develops ASICs and FPGAs for cutting edge satellites systems that deliver unprecedented quantities of data at unheard of speeds to the service-members who defend our Nation and Allies. From initial design through on-orbit operations this lead is responsible for leading a phenomenal team of engineers in a collaborative effort to design, manufacture, test and operate chips for satellites that make our Nation safer.

Requirements

Bachelor’s degree in electrical engineering, computer engineering, computer science, or another engineering discipline.
5+ years of experience in RTL implementation and/or FPGA/ASIC development.
2+ years of experience with direct report management or mentoring an engineering team.

Nice To Haves

Experience solving problems including clock domain crossings and power optimization.
Experience developing complex ASICs.
Experience with multicore CPU subsystem design.
Experience with standard bus protocols (e.g. AXI, AHB, etc.).
Experience with embedded processors.
Experience with high speed and low power design techniques.
Scripting skills (Python, TCL etc.).
Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass) and FPGA tools (e.g. Xilinx Vivado, Altera Quartus II).
Ability to work in a dynamic environment with changing needs and requirements.
Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis.
Enjoy being challenged and learning new skills.

Responsibilities

Lead a small team responsible for the digital design of ASICs and/or FPGAs for Starshield projects.
Lead architectural trades for features, performance requirements and system limitations. Derive specifications for the subsystems and circuits, and work with modem/DSP and RFIC engineers to partition functions between hardware and software domains.
Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design.
Work closely with verification team to ensure all aspects of the design are covered and verified.
Work with leaders across the engineering organization to drive product requirements to push the performance envelope for Starshield satellites.
Recruit, develop, train, and retain world class team members who will deliver for our Nation and amplify the team.
Provide timing constraints for those IPs and support the physical implementation team (synthesis, timing closure, formality check).
Participate in silicon bring-up and validation. Assist in the development of automated test lab equipment for lab measurements.

Benefits

comprehensive medical, vision, and dental coverage
access to a 401(k) retirement plan
short and long-term disability insurance
life insurance
paid parental leave
various other discounts and perks
3 weeks of paid vacation
10 or more paid holidays per year
paid sick leave
company stock or long-term cash awards
potential discretionary bonuses
ability to purchase additional stock at a discount through an Employee Stock Purchase Plan