Digital ASIC Design Manager

Keysight Technologies, Inc.•Colorado Springs, CO

19h•$151,000 - $253,000•Onsite

About The Position

Keysight is a leader in technology innovation, providing solutions in electronic design, simulation, prototyping, test, manufacturing, and optimization across various markets including communications, automotive, energy, and semiconductor. With approximately 15,000 employees, Keysight serves customers in over 100 countries. The company fosters an award-winning culture that encourages creativity and innovation. This specific role is within Keysight Laboratories, a key technology organization responsible for developing breakthrough solutions. The team focuses on designing and delivering next-generation Digital ASICs, which are crucial for Keysight's success and provide significant customer value. The role is based in Colorado Springs, offering a purpose-built development campus with on-site fitness and recreation, and access to outdoor activities and a high quality of life.

Requirements

B.S. or M.S. in Electrical Engineering, Computer Engineering, or equivalent practical experience.
7+ years of digital IC/ASIC development experience, with demonstrated progression in technical leadership (people management experience preferred).
Strong hands-on depth in RTL micro-architecture and implementation (SystemVerilog/Verilog/VHDL), synthesis, STA/timing closure, and power/performance optimization.
Deep expertise in modern verification, including constrained-random methodology, formal techniques, and acceleration/emulation.
Working knowledge of the full silicon lifecycle and cross-functional handoffs, including physical design, DFT/scan, signoff flows, and foundry enablement.
Proven ability to deliver complex programs to tapeout—building credible plans, managing dependencies and risk, and driving alignment across multiple teams.
Proficiency with industry-standard EDA environments (e.g., Cadence and Siemens/Mentor) and productivity scripting/automation (Python, Tcl, and/or Ruby).
Executive-level communication skills and strong stakeholder management—able to translate technical trade-offs into clear decisions and commitments.
Sound judgment under schedule pressure, with a track record of prioritizing the right trade-offs while maintaining quality.
Demonstrated people leadership strengths, including mentoring and coaching engineers, developing technical leaders, and building a strong team culture of accountability, learning, and engineering excellence.

Responsibilities

Set and drive the technical strategy for digital IP, block-level design, verification, and full-chip integration—aligning architectural choices to product differentiation, schedule, and long-term reuse.
Lead, mentor, and scale a high-performing organization of architects, RTL designers, and verification engineers; establish clear technical expectations and a culture of ownership and excellence.
Own program delivery from concept through tapeout and into productization—planning resources, managing schedules and milestones, and proactively driving risk retirement and trade-off decisions.
Influence outcomes across the broader silicon ecosystem by partnering tightly with physical design, DFT/test, IP, software/firmware, packaging, systems engineering, and foundry/OSAT partners.
Establish and enforce robust quality and signoff discipline, including design reviews, coding standards, verification closure, timing and power closure, area/constraints management, and manufacturability/yield considerations.
Build a world-class team: recruit and hire top talent, develop technical leaders, and manage performance and career growth to retain key capabilities.
Manage the operating model for the team, including budget ownership, EDA/tool strategy, license planning, and vendor/partner selection.
Drive continuous improvement in productivity and predictability through design flows, automation, CI/regression infrastructure, and disciplined IP reuse strategies.