About The Position

The Lead ASIC Design Verification Engineer will lead a team that supports custom ASICs and FPGAs design for cutting edge satellites systems that deliver unprecedented quantities of data at unheard of speeds to the service-members who defend our Nation and Allies. From initial design through on-orbit operations this person is responsible for leading a phenomenal team of engineers in a collaborative effort to design, manufacture, test and operate chips for satellites that make our Nation safer.

Requirements

  • Bachelor’s degree in electrical engineering, computer engineering, computer science, or another engineering discipline.
  • 4+ years of experience with design verification and test bench development.

Nice To Haves

  • Advanced degree in electrical engineering or computer engineering.
  • Experience with verification methodologies such as UVM/OVM/VMM.
  • Strong object-oriented programming knowledge.
  • Strong problem-solving and coding skills.
  • Experience in constrained random verification.
  • Expertise in developing test plans, implementing coverage models, and analyzing results.
  • Experience with scripting languages, e.g. Python for automation.
  • RTL design, chip bring-up, and post-silicon validation experience.
  • Ability to work in a dynamic environment with changing needs and requirements.
  • Ability to work in a dynamic environment with changing needs and requirements.
  • Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis.
  • Enjoy being challenged and learning new skills.

Responsibilities

  • Lead a team responsible for digital ASIC verification at block and system level.
  • Lead and execute verification test plan, development, and milestones from beginning to end, develop test harnesses and test sequences.
  • Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs, including DSP blocks.
  • Responsible for overseeing test plan execution, running regressions, code and functional coverage closure.
  • Contribute to pre-silicon verification, chip bring-up and post-silicon validation.
  • Work with leaders across the engineering organization to drive product requirements to push the performance envelope for Starshield satellites.
  • Recruit, develop, train, and retain world class team members who will deliver for our Nation and amplify the team.

Benefits

  • comprehensive medical, vision, and dental coverage
  • access to a 401(k) retirement plan
  • short and long-term disability insurance
  • life insurance
  • paid parental leave
  • various other discounts and perks
  • 3 weeks of paid vacation
  • 10 or more paid holidays per year
  • paid sick leave
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