ASIC Design Engineer

Celero Communications, Inc.

6h

About The Position

We are seeking a highly experienced ASIC Design Engineer to play a critical technical leadership role in the development of next-generation semiconductor products. In this role, you will architect, design, and implement complex digital blocks and subsystems in RTL, delivering high-quality, production-ready silicon. You will operate as a technical authority within the digital design organization, owning major functional blocks from concept through tape-out, and working closely with architecture, verification, physical design, and systems teams. This role is ideal for a senior individual contributor who thrives on solving complex design challenges, mentoring other engineers, and shaping design methodologies.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of experience in RTL design and digital implementation.
• Proven ownership of multiple successful tape-outs.
• Strong hands-on expertise in SystemVerilog / Verilog.
• Strong hands-on expertise in Digital design and micro-architecture.
• Strong hands-on expertise in Synthesis and timing-aware design.
• Solid understanding of Clock domain crossing (CDC).
• Solid understanding of Reset strategies.
• Solid understanding of Low-power design techniques.

Nice To Haves

• Experience with complex SoCs (AI, networking, CPU/GPU, storage).
• Familiarity with UVM-based verification.
• Familiarity with Formal verification.
• Familiarity with DFT concepts.
• Knowledge of High-speed interfaces (PCIe, Ethernet, DDR, HBM).
• Knowledge of Power management (UPF, power gating).
• Experience in advanced nodes (7nm and below).

Responsibilities

• Architect and implement complex digital blocks using SystemVerilog/Verilog.
• Define micro-architecture, pipelines, and interfaces.
• Translate system and architectural requirements into efficient RTL designs.
• Ensure designs meet performance, power, and area (PPA) targets.
• Act as technical lead for critical RTL subsystems.
• Mentor and guide junior and senior RTL engineers.
• Lead design reviews and drive architectural decisions.
• Establish and promote RTL coding standards and best practices.
• Partner closely with system architects, verification engineers, physical design and DFT teams, and firmware and software teams.
• Provide early feasibility analysis and implementation feedback.
• Support integration and top-level chip bring-up.
• Work with verification teams to define verification strategies.
• Develop reference models and test vectors as needed.
• Ensure functional correctness, robustness, and maintainability.
• Drive closure of design issues and bugs.
• Support first silicon bring-up and lab debug.
• Analyze silicon behavior and correlate with RTL.
• Drive ECOs and fixes for post-silicon issues.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior