ASIC Physical Design Manager

Keysight Technologies, Inc.•Colorado Springs, CO

19h•$151,000 - $253,000•Onsite

About The Position

Keysight is at the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~15,000 employees create world-class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Our award-winning culture embraces a bold vision of where technology can take us and a passion for tackling challenging problems with industry-first solutions. We believe that when people feel a sense of belonging, they can be more creative, innovative, and thrive at all points in their careers. This role sits within Keysight Laboratories—a globally recognized technology organization that enables Keysight to be first to market with breakthrough, highly differentiated solutions. Our team of senior engineers has delivered generations of innovation across ASIC and product development, spanning the breadth of the technology landscape. You’ll join a high-performance, globally connected engineering organization designing and delivering next-generation Digital and Mixed signal ASICs. A sustained driver of Keysight’s success is the creation and deployment of breakthrough digital and mixed-signal ASICs that unlock step-function performance and customer value in new products. We are seeking an ASIC Physical Design R&D Manager to lead our ASIC Physical Design team—overseeing end-to-end physical implementation and ensuring designs meet aggressive performance, power, and area targets through tapeout and into product development. The position is based in Colorado Springs at the foot of Pikes Peak, with a purpose-built development campus that brings engineering, advanced technology development, assembly, and machining together in one location. Outside the lab, the campus supports an active lifestyle with on-site fitness and recreation, and Colorado Springs offers exceptional quality of life—immediate access to world-class outdoor activities, year-round recreation, and more than 300 days of sunshine each year.

Requirements

B.S. or M.S. in Electrical Engineering or Computer Engineering (or equivalent experience).
7+ years of relevant experience in digital ASIC physical design, including successful tape releases.
5+ years of project/program management experience, including planning, dependency management, risk tracking, and cross-team execution to tapeout.

Nice To Haves

Demonstrated people leadership, including mentoring and coaching engineers, developing future technical leaders, and building an inclusive, high-accountability culture.
Expertise in physical implementation and layout methodology, including timing closure, signoff, and power/performance/area optimization.
Working knowledge of DFT methodologies (e.g., scan insertion/test considerations) and how they impact physical design, closure, and tape release.
Strong EE fundamentals with experience spanning ASIC design concepts, IP integration, and CMOS/BiCMOS processes.
Strong teamwork and problem-solving skills, with clear written and verbal communication across engineering and program stakeholders.
Leadership skills to drive change and influence cross-functional teams toward execution goals, quality, and predictable delivery.
Sound technical judgment under schedule pressure, with a track record of making effective PPA trade-offs while maintaining signoff quality.

Responsibilities

Drive the physical design technical strategy across programs, including floorplanning, power architecture, and implementation trade-offs to meet PPA (performance, power, area) targets.
Lead, mentor, and grow a high-performing Physical Design team; set clear expectations for technical rigor, execution, and delivery.
Oversee physical implementation for digital, mixed-signal, and third-party IP—from block to subsystem to top-level integration—including place and route, timing closure, and power closure.
Coordinate closely with RTL/design, DFT/test, packaging, and systems teams to ensure clean handoffs, rapid issue resolution, and aligned delivery through tapeout.
Own and continuously improve the Physical Design flow, including methodology, automation, CI/regression infrastructure, and best-practice enablement for predictability and quality.
Lead physical verification and signoff (DRC/LVS, STA, power/IR/EM, reliability as applicable) and drive tape release readiness with clear signoff criteria.
Serve as the primary physical design interface to external CMOS/BiCMOS foundries and partners, ensuring alignment on PDKs, signoff requirements, and tapeout execution.
Own project execution across the physical design lifecycle—planning, resourcing, schedules, milestones, and risk mitigation—to deliver predictable tapeouts and product readiness.