Implementation Timing / STA Design Engineer

Qualcomm•San Diego, CA

3d•$140,000 - $210,000

About The Position

Qualcomm’s SoC Implementation Team is looking for skilled engineers to focus on timing constraints development, power analysis, STA, and timing closure for premium-tier chips. This is an excellent opportunity to join the Snapdragon implementation team, which is responsible for SoCs in sub-3nm nodes across mobile, AI, and automotive sectors. Candidates should have at least 2 years of experience and be proficient with tools such as Primetime, Fishtail/TCM. Scripting skills in Tcl, Perl, or Python are also desirable.

Requirements

Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Proficiency with tools such as Primetime, Fishtail/TCM.
Scripting skills in Tcl, Perl, or Python are also desirable.

Responsibilities

Develop constraints for physical power-aware synthesis, setup for various modes/corners and low-power multi-voltage domain crossings, and signoff with static timing analysis.
Collaborate closely with RTL design and physical design teams to identify timing requirements and bottlenecks.
Generate/review, and validate clock domain crossing and design constraints to achieve timing closure of complex SoC cores.
Review and integrate HM constraints into SoC and ensure correlation between HM and SoC timing.
Analyze timing across modes and corners, understand concepts like path pessimism and margins.