High Speed IO (HSIO) Validation Engineer

Advanced Micro Devices, Inc • Santa Clara, CA

2d

About The Position

The High-Speed IO (HSIO) Validation Engineer validates and debugs high-speed interfaces across CPU and GPU platforms, including data center servers and AI systems. The role works closely with PHY design, signal integrity/power integrity (SI/PI), firmware, and platform teams to execute validation plans, characterize interface performance, and investigate silicon- and system-level issues. The engineer helps ensure product quality and readiness for AMD technologies.

The position includes executing validation and compliance activities for current and emerging high-speed interfaces; supporting post-silicon bring-up, characterization, margining, and interoperability validation; performing electrical- and protocol-level debug with lab equipment; and analyzing signal integrity, power integrity, and link-training behavior. It also involves developing automation and analysis tools, documenting findings and recommendations, communicating status to stakeholders, and improving validation methodologies and lab infrastructure. The role is located in Santa Clara, California and is not eligible for visa sponsorship.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field, with 5+ years of experience in high-speed IO, silicon validation, system validation, or related areas.
• Experience with high-speed serial interfaces such as PCIe, CXL, Ethernet, UALink, or similar technologies.
• Strong understanding of signal integrity concepts, channel characteristics, equalization techniques (CTLE, DFE, TX FIR), and link-level behavior.
• Experience with lab bring-up, validation, and debug using high-speed measurement equipment such as oscilloscopes, BERTs, VNAs, and protocol analyzers.
• Strong programming and scripting skills in Python, C/C++, or similar languages for automation and data analysis.
• Familiarity with silicon bring-up, compliance testing, and system-level debug methodologies.
• Strong analytical and problem-solving skills, with the ability to drive technical issues to resolution.
• Effective communication and collaboration skills within cross-functional engineering teams.
• Bachelor’s, Master’s, or PhD degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent.

Nice To Haves

• Experience validating server, AI, networking, or accelerator platforms.
• Experience with PCIe, Ethernet, UALink, or other high-speed interface compliance and interoperability testing.
• Experience developing automated validation frameworks and data-analysis workflows.
• Contributions to technical publications, patents, industry standards, or internal best-known methods (BKMs).
• Strong commitment to quality, innovation, teamwork, and continuous improvement.

Responsibilities

• Execute validation plans for high-speed IO interfaces, including PCIe Gen5/Gen6/Gen7, UALink, xGMI, Ethernet, and emerging technologies.
• Support post-silicon bring-up, characterization, compliance testing, margining, and interoperability validation across multiple platforms.
• Collaborate with design, architecture, firmware, board, and test teams to investigate and resolve high-speed interface issues.
• Develop and enhance test automation, validation scripts, and data-analysis tools to improve validation efficiency and coverage.
• Perform electrical- and protocol-level debug using oscilloscopes, BERTs, protocol analyzers, and other lab equipment.
• Analyze signal integrity, power integrity, and link-training behavior to identify root causes and drive corrective actions.
• Document validation findings, debug results, and recommendations, and communicate status to project stakeholders.
• Contribute to continuous improvement of validation methodologies, best-known methods (BKMs), and lab infrastructure.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level