HBM Design Architect
About The Position
Micron Technology’s High Bandwidth Memory (HBM) Design Architecture team develops memory solutions for AI accelerators, high-performance computing, and data centers. The Roadmap and Pathfinding group works across device technology, process, packaging, and product architecture to enable next-generation memory technologies for product intercept. The HBM Design Architect leads the technical enablement of novel memories and integration technologies, including DRAM, gain-cell memory, stacked DRAM, and scaled-pitch hybrid bonding. The role uses an understanding of mainstream DRAM and HBM products to translate technology capabilities into product architectures, identify product requirements at risk, and develop de-risking plans with design, process, packaging, and product teams.
Requirements
- Bachelor’s degree in Electrical Engineering, Physics, Materials Science, or a related field with at least 7 years of relevant experience; master’s degree with at least 5 years; or PhD with at least 3 years.
- Solid grounding in mainstream DRAM and/or HBM product architecture and design, including array, periphery, datapath, timing, and power.
- Deep understanding of DRAM or emerging-memory cell and array operation, including sensing, retention, disturb, and variability.
- Working knowledge of semiconductor process technology and its impact on device and circuit behavior.
Nice To Haves
- PhD or equivalent experience with at least 10 years in DRAM/HBM build, memory technology, or pathfinding.
- Direct experience with vertically coordinated DRAM technologies, gain-cell structures such as 2T0C/IGZO or similar, stacked memory builds, or other emerging-memory programs.
- Experience with hybrid bonding, TSV-based 3D integration, or advanced packaging technology development.
Responsibilities
- Lead architecture and feasibility assessments for emerging memories, including DRAM, gain cell, and stacked or vertical DRAM, as well as advanced integration such as hybrid bonding and fine-pitch TSV.
- Apply mainstream DRAM/HBM product knowledge—including array architecture, timing parameters, bandwidth, power, RAS, and JEDEC requirements—to define product-viability requirements for new technologies.
- Translate device and process characteristics, including retention, variability, cell and array physics, BEOL, and bonding constraints, into product-level requirements for bandwidth, latency, power, thermals, density, and reliability.
- Identify technology–product gaps, define technology targets, and drive de-risking plans involving test vehicles, DOEs, and modeling or simulation strategies.
- Partner with process integration, device, packaging, and design teams to define technology-to-product intercept points and decision criteria.
- Lead system-technology co-optimization (STCO) studies across array architecture, periphery/CMOS-under-array, interconnect, PDN, and thermal trade-offs.
- Develop roadmap proposals and present recommendations to technical leadership and cross-site working groups.
Benefits
- Choice of medical, dental, and vision plans.
- Programs that help protect income in case of illness or injury.
- Paid family leave.
- Paid time-off program.
- Paid holidays.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
