Gate-level Noise (Signal Integrity) / STA CAD Engineer

Apple•Austin, TX

About The Position

As a member of Apple’s CAD group, the engineer supports gate-level glitch-noise and static timing analysis (STA) methodologies that ensure signal integrity and robustness of Apple silicon across advanced technology nodes. The role involves applying sign-off methodologies, margin models, and production CAD flows for crosstalk glitch and timing closure using industry-standard tools. The engineer works closely with CAD and physical design teams, assists with tool qualification, supports tapeout ECO tasks, and uses modern automation, including AI-agent workflows, to scale analysis across large SoC designs. The role defines and deploys noise and STA analysis methodologies, margins, and tool/version qualification strategies; owns analysis flows and scripts from constraint setup through sign-off; investigates noise violations and timing-path anomalies; and serves as a technical contact for design and Physical Design teams. It also advances analysis automation and AI-assisted workflows, builds infrastructure for report mining and visualization, supports noise and timing ECOs, documents methodologies, and mentors junior engineers.

Requirements

BS in Electrical Engineering, Computer Engineering, or a related technical discipline.
10+ years of industry experience.

Nice To Haves

Hands-on experience with signal integrity analysis tools such as Tempus, PrimeTime-SI, ETS/Celtic, or equivalent.
Strong understanding of STA fundamentals and PrimeTime specifics, including Tcl coding, attributes, commands, and reports.
Strong Perl, Tcl, and/or Python scripting skills and a systematic debugging approach.
Working knowledge of crosstalk, OCV effects, margins, constraints, aggressor selection, and correlation basics.
BS or MS in a technical discipline.
Ability to plan and execute tool/methodology evaluations and qualify a new tool or tool version systematically and repeatably.
Exposure to transistor-level analysis and SPICE simulation.
Expertise in AI/ML-driven and agentic-workflow innovation for CAD and noise/timing flows, including LLM-based triage, debug-copilot workflows, and agent-based report mining.
Experience wrapping existing Perl/Tcl flow scripts as callable tools within an agent framework for natural-language-driven flow operations.
Familiarity with noise and timing ECO techniques and implementation.
Excellent communication and presentation skills, with the ability to coordinate initiatives with design teams and CAD groups with little to no oversight.

Responsibilities

Define and architect consistent noise and STA analysis methodology, margins, and tool/version qualification strategy, and drive deployment across multiple projects with minimal oversight.
Own and drive flows and scripts for core gate-level noise and static timing analysis tools end to end, from constraint setup through sign-off, including automation, quality metrics, and continuous improvement.
Conduct root-cause analysis of noise violations and timing-path anomalies, including use of LLM-agent pipelines to triage and classify failures.
Serve as the technical authority and primary point of contact for design and Physical Design teams on noise/timing constraints, flows, and closure issues, and surface best practices.
Drive noise and STA methodology improvements using AI coding agents to prototype and harden analysis methodologies, margin models, and waiver-justification logic.
Build infrastructure for large-scale noise/timing report mining, QoR extraction, and visualization, including agent- or retrieval-backed natural-language queries over report corpora.
Develop and support noise and timing ECO methodology and custom scripts for project tapeout.
Apply agentic diffing and summarization to accelerate tool and version qualification and flag regressions, while retaining human judgment on sign-off decisions and waivers.
Create documentation, guidelines, and specifications that can also provide grounding context for internal AI assistants.
Mentor junior engineers on noise/STA analysis techniques and best practices.
Assist with tool qualifications and execute tapeout ECO tasks.