Gate-level Noise (Signal Integrity) / STA CAD Engineer

Apple • Austin, TX

8d

About The Position

As a member of Apple’s CAD group, the Gate-level Noise (Signal Integrity) / STA CAD Engineer supports gate-level glitch-noise and static timing analysis (STA) methodologies that ensure the signal integrity and robustness of Apple silicon across advanced technology nodes. The role applies sign-off methodologies, margin models, and production CAD flows for crosstalk glitch and timing closure using industry-standard tools, and works with CAD and physical design teams on tool qualification, tapeout ECO tasks, and automation, including AI-agent workflows for analysis across large SOC designs.

The position owns noise and STA analysis flows, scripts, methodologies, and infrastructure from constraint setup through sign-off. It includes root-cause analysis of noise violations and timing anomalies, improvements to reporting and automation, development of ECO methods, documentation, and support for project teams. The role also uses AI coding agents and agentic workflows to prototype and improve analysis, triage, report mining, tool qualification, and documentation, while retaining human judgment for sign-off decisions and waivers. It mentors junior engineers and serves as a technical contact for design and Physical Design teams.

Requirements

• BS in Electrical Engineering, Computer Engineering, or a related technical discipline; the posting also lists BS or MS in a technical discipline.
• 10+ years of industry experience.
• Hands-on experience with signal integrity analysis tools such as Tempus, PrimeTime-SI, ETS/Celtic, or equivalent.
• Strong understanding of STA fundamentals and PrimeTime specifics, including Tcl coding, attributes, commands, and reports.
• Strong Perl, Tcl, and/or Python scripting skills and a systematic debugging approach.
• Working knowledge of crosstalk, OCV effects, margins, constraints, aggressor selection, and correlation basics.
• Ability to plan and execute tool/methodology evaluations and qualify a new tool or tool version systematically and repeatably.
• Excellent communication and presentation skills, with the ability to coordinate initiatives with design teams and CAD groups with little to no oversight.

Nice To Haves

• Exposure to transistor-level analysis and SPICE simulation.
• Expertise in AI/ML-driven and agentic-workflow innovation for CAD and noise/timing flows, including LLM-based triage, debug-copilot workflows, and agent-based report mining.
• Experience wrapping existing Perl/Tcl flow scripts as callable tools within an agent framework for natural-language-driven flow operations.
• Familiarity with noise and timing ECO techniques and implementation.

Responsibilities

• Define and architect consistent noise and STA analysis methodology, margins, and tool/version qualification strategy, and drive deployment across multiple projects with minimal oversight.
• Own and drive flows and scripts for core gate-level noise and static timing analysis tools end to end, from constraint setup through sign-off, including automation, quality metrics, and continuous improvement.
• Conduct root-cause analysis of noise violations and timing-path anomalies, using LLM-agent pipelines to help triage and classify failures.
• Serve as a technical authority and primary point of contact for design and Physical Design teams on noise/timing constraints, flows, and closure issues, and surface best practices.
• Drive noise and STA methodology improvements, using AI coding agents to prototype and harden analysis methodologies, margin models, and waiver-justification logic.
• Build infrastructure for large-scale noise/timing report mining, QoR extraction, and visualization, including agent- or retrieval-backed natural-language queries over report corpora.
• Develop and support noise and timing ECO methodology and custom scripts for project tapeout.
• Use agentic diffing and summarization to accelerate tool and version qualification and flag regressions, while retaining human-in-the-loop judgment on sign-off decisions and waivers.
• Create documentation, guidelines, and specifications that can also provide grounding context for internal AI assistants.
• Mentor junior engineers on noise/STA analysis techniques and best practices.
• Plan and execute tool and methodology evaluations, including systematic and repeatable qualification of new tools or tool versions.
• Coordinate initiatives with design teams and CAD groups.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior