Gate-level Noise (Signal Integrity) / STA CAD Engineer

Apple • Austin, TX

8d

About The Position

As a member of Apple’s CAD group, the Gate-level Noise (Signal Integrity) / STA CAD Engineer supports gate-level glitch noise and static timing analysis (STA) methodologies that ensure the signal integrity and robustness of Apple silicon across advanced technology nodes. The role applies sign-off methodologies, margin models, and production CAD flows for crosstalk glitch and timing closure using industry-standard tools, with guidance from senior engineers.

The engineer works closely with CAD and physical design teams, assists with tool qualifications, supports tapeout ECO tasks, and contributes to automation—including AI-agent workflows—to scale analysis across large SOC designs. The position also involves developing and maintaining production flows and scripts, supporting root-cause analysis and design convergence, and documenting and sharing best practices.

Requirements

• Bachelor of Science in Electrical Engineering, Computer Engineering, or a related technical discipline.
• At least 3 years of industry experience.

Nice To Haves

• Background in gate-level signal integrity, especially crosstalk glitch noise and static timing analysis (STA).
• Hands-on experience with industry-standard SI and STA tools such as PrimeTime-SI, Tempus, or equivalent.
• Exposure to noise and timing sign-off on advanced process nodes.
• Experience with or exposure to noise and timing ECO flows and design-closure techniques.
• Scripting and automation skills in Python, Tcl, and/or Perl.
• Ability to coordinate and drive initiatives with appropriate guidance.
• Familiarity with standard-cell library noise characterization (such as CCSN) or correlating gate-level models with SPICE simulations.
• Understanding of place-and-route (P&R) implementation engines and physical design convergence.
• Interest in AI/LLM-assisted workflows for CAD scripting, report parsing, or automated triage.
• Strong communication and presentation skills.

Responsibilities

• Contribute to sign-off methodologies, noise margins, and tool qualification strategies for gate-level glitch noise and STA across advanced nodes.
• Develop and maintain production CAD flows and scripts for core noise and STA tools, from constraint setup through tapeout sign-off.
• Support glitch noise analysis, including glitch thresholds, propagation, and impacts on timing and functional integrity.
• Support root-cause analysis of crosstalk glitch and timing anomalies; use and help build automated triage workflows and AI-agent pipelines to improve debug efficiency.
• Collaborate with and support design and physical design teams on noise and timing constraints, flow issues, and sign-off waivers.
• Support noise and timing ECO methodologies to help accelerate design convergence toward tapeout.
• Participate in systematic tool and version qualifications, tracking QoR, performance, and correlation against golden baselines.
• Help author documentation and guidelines and share noise and STA best practices with the team.
• Assist with tool qualifications and execute tapeout ECO tasks.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level