Gate-level Noise (Signal Integrity) / STA CAD Engineer

Apple • Austin, TX

8d

About The Position

As a member of Apple’s CAD group, the engineer will support gate-level glitch noise and static timing analysis (STA) methodologies that ensure the signal integrity and robustness of Apple silicon across advanced technology nodes. Under the guidance of senior engineers, the role involves learning and applying sign-off methodologies, margin models, and production CAD flows for crosstalk glitch and timing closure using industry-standard tools. The engineer will work with CAD and physical design teams, assist with tool qualifications, help execute tapeout ECO tasks, and gain exposure to automation, including AI-agent workflows, used to scale analysis across large SOC designs.

Requirements

• Bachelor of Science in Electrical Engineering, Computer Engineering, or a related technical discipline.
• Good communication skills and eagerness to learn.

Nice To Haves

• 1–2 years of experience in CAD methodology, EDA support, or digital design.
• Foundational understanding of gate-level signal integrity concepts, including crosstalk glitch noise and static timing analysis (STA).
• Exposure to industry-standard SI and STA tools such as PrimeTime-SI, Tempus, or equivalent through coursework, internship, or self-study.
• Basic scripting skills in Python, Tcl, and/or Perl.
• Willingness to learn noise and timing sign-off and ECO concepts with team support.
• Ability to execute well-defined tasks with close guidance and mentorship.
• Coursework or project exposure to standard cell library noise characterization, such as CCSN, or SPICE simulation basics.
• Familiarity with place-and-route (P&R) concepts and physical design flow basics.
• Curiosity about AI/LLM-assisted workflows for CAD scripting, report parsing, or automated triage.

Responsibilities

• Assist with established sign-off methodologies, noise margins, and tool qualification procedures for gate-level glitch noise and STA.
• Run and maintain production CAD flows and scripts for core noise and STA tools, supporting constraint setup through tapeout sign-off.
• Assist with glitch noise analysis, including checking glitch thresholds and propagation reports under supervision.
• Assist with root-cause analysis of crosstalk glitch and timing anomalies using established automated triage workflows and AI-agent pipelines.
• Work with design and physical design teams on noise/timing constraints and flow issues, escalating closure and waiver decisions to senior engineers.
• Help execute noise and timing ECO tasks to support design convergence toward tapeout.
• Participate in tool and version qualification activities and help track QoR and performance data against golden baselines.
• Help maintain documentation and learn noise and STA best practices from the team.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level