FPGA Verification Engineer Level 3/4 - Linthicum

Northrop Grumman•Linthicum Heights, MD

2d•$119,600 - $223,900•Onsite

About The Position

Northrop Grumman Space Systems is seeking a Principal Digital Verification or Senior Principal Digital Verification Engineer for the development of digital subsystems and products. Northrop Grumman Space Systems Electronics & Payload is a leading global supplier of Space systems. The Digital Technology department develops subsystems and products to deliver advanced operational capabilities on schedule and under budget. In this position the Verification Engineer will be responsible for ensuring the correctness and functionality of digital designs, typically used in integrated circuits (ICs) or digital systems, before they are manufactured. Their primary task is to verify that the design meets the necessary specifications and operates as intended, identifying and correcting potential issues early in the design process. These digital systems digital subsystems can be used in radar, Electro Optical, Electronic Warfare and other sensor and processing applications. Northrop Grumman is currently seeking FPGA Verification Engineers Level 3 or 4 for our Linthicum, Maryland location. This position can be filled at either level depending upon years of experience and qualifications.

Requirements

Bachelor’s degree with 5 years of experience; or a master’s degree with 3 years of related experience; or a PhD with 0 years of experience in Electrical Engineering, Computer Engineering, Computer Science, or related technical fields (Level 3)
3 years of experience with FPGA verification using VUnit.
Experience with the use of various FPGAs or the development of HDL (Verilog, SystemVerilog and VHDL) code within the corresponding IDE
Must be a U.S. citizen
No clearance required to start, but must be able to obtain and maintain a DoD Secret or Top-Secret Clearance per business requirements
Experience developing test plans, participating in reviews, test development and RTL debug
Bachelor’s degree with 8 years of experience, a master’s degree with 6 years of experience or a PhD with 3 years of experience in Electrical Engineering, Computer Engineering, Computer Science, or related technical fields (Level 4).
Proficiency in hardware description languages (e.g., SystemVerilog, Verilog, VHDL).
Familiarity with industry-standard tools (e.g., Synopsys, Mentor Graphics).
3+ years of experience with FPGA verification using VUnit.
Digital subsystem, ASIC, FPGA and/or digital board development experience and knowledge essential
Candidate must have good communication skills, strong interpersonal skills, and good oral and written presentation skills
Must be able to mentor and coach early career Engineers as needed
Must be a U.S. citizen
No clearance required to start, but must be able to obtain and maintain Secret or Top-Secret level security clearance, per business requirements
Experience developing test plans, participating in reviews, test development and RTL debug

Nice To Haves

Active DoD Top Secret Clearance or higher and/or SCI eligibility
Experience with data structures, object-oriented programming languages and concepts
Experience with Verification IP integration and/or development
Experience with a coverage-driven verification methodology from planning through closure
Experience in creating comprehensive documentation of test cases, verification plans/methods, and test results for review and future reference.
Knowledge of industry standard bus or I/O interfaces
Experience with SystemVerilog Assertions (SVA)
Experience with VHDL Assertions
FPGA/ASIC design and/or development process experience
Experience with scripting languages (Bash, Perl, Python, Tcl, Makefile)
Knowledge of digital signal processing
Knowledge of working with Xilinx and MicroChip FPGAs (Kintex, Zynq ultrascale+, RTG4, etc)
Effective communication with systems and software teams for requirements, ICDs, handoffs, etc.
Able to work effectively within a development team to understand system level inter-dependence and design constraints

Responsibilities

Work closely with design and other verification engineers and will utilize your knowledge of modern verification methods, tools and techniques.
Perform functional verification of register transfer level (RTL) code of a complex FPGA at block level and SOC level using VUnit.
Development of testbench, tests, verification IP (VIP), verification models, coverage models, extensive simulation and debug, code coverage and functional coverage, generation and analysis of reports and metrics, documentation etc.
Develop a verification plan based on design specifications and requirements.
Analyze failures from test simulations, find the root causes of bugs, and work with designers to resolve issues
Automate and perform regression testing to ensure new changes don’t break existing functionality
Ability to operate in a team environment and collaborate across the different teams as required to accomplish the design goals.